VLSI Questions and Answers – Wiring Capacitances

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Wiring Capacitances”.

1. Which contributes to the wiring capacitance?
a) fringing fields
b) interlayer capacitance
c) peripheral capacitance
d) all of the mentioned

Explanation: The sources of capacitances that contribute to the total wiring capacitance are fringing field capacitance, interlayer capacitance and peripheral capacitance.

2. What does the value d in fringing field capacitance measures?
a) thickness of wire
b) length of the wire
c) wire to substrate separation
d) wire to wire separation

Explanation: The quantity d in fringing field capacitance measures the wire to substrate separation. It is the distance between the wire and the substrate used in the device.

3. Total wire capacitance is equal to ___________
a) area capacitance
b) fringing field capacitance
c) area capacitance + fringing field capacitance
d) peripheral capacitance

Explanation: Total wire capacitance can be given as the sum of area capacitance and fringing field capacitance.

4. Interlayer capacitance occurs due to ___________
a) separation between plates
b) electric field between plates
c) charges between plates
d) parallel plate effect

Explanation: Interlayer capacitance occurs due to a parallel plate effect between one layer and another. When one capacitance value comes closer to another they create some combined effects.

5. Which capacitance must be higher?
a) metal to polysilicon capacitance
b) metal to substrate capacitance
c) metal to metal capacitance
d) diffusion capacitance

Explanation: Metal to polysilicon capacitance should be higher than metal to substrate capacitance. This is due to that when one layer underlies the other and in consequence interlayer capacitance is highly dependent on layout.
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6. Peripheral capacitance is given in _________ eper unit length.

Explanation: Peripheral capacitance is given in picofarads per unit length. This is the sidewall capacitance. Each diode has this side wall capacitance.

7. For greater relative value of peripheral capacitance ___________ should be small.
a) source area
b) drain area
c) source & drain area
d) none of the mentioned

Explanation: The smaller the source or drain area, the greater the relative value of peripheral capacitance as they are both inversely related.

8. Diffusion capacitance is equal to ___________
a) area capacitance
b) peripheral capacitance
c) fringing field capacitance
d) area capacitance + peripheral capacitance

Explanation: Diffusion capacitance is given by the sum of area capacitance and peripheral capacitance.

9. Polysilicon is suitable for ___________
a) small distance
b) large distance
c) all of the mentioned’
d) none of the mentioned

Explanation: Polysilicon is unsuitable for routing Vdd or Vss other than for very small distance because of the relatively high Rs value of the polysilicon layer.

10. Which has a high voltage drop?
a) metal layer
b) polysilicon layer
c) diffusion layer
d) silicide layer

Explanation: Polysilicon layer has high voltage drop. It has a moderate RC product.

11. Which layer has high capacitance value?
a) metal
b) diffusion
c) silicide
d) polysilicon

Explanation: Diffusion or active layer has high capacitance value due to which it has low or moderate IR drop.

12. Which layer has high resistance value?
a) polysilicon
b) silicide
c) diffusion
d) metal

Explanation: Polysilicon layer has high resistance value and due to this it has high IR drop.

13. While measuring the output load capacitance Cgs, n and Cgs, p is not considered. Why?
a) Because Cgs, n and Cgs, p are the capacitances at the input nodes
b) Because Cgs, n and Cgs, p does not exist during the operation of CMOS inverter
c) Because Cgs, n and Cgs, p are storing opposite charges and cancel out each other during the calculation of load capacitance
d) None of the mentioned

Explanation: Cgs, n and Cgs, p are gate to source capacitances of nMOS and pMOS transistors in CMOS inverter. They are measured at input node. Therefore they are not considered for calculation of load capacitance.

14. During the calculation of load capacitance of a 1st stage CMOS inverter, the input node capacitances, Cgs, n and Cgs, p of the 2nd stage CMOS inverter is also considered.
a) True
b) False

Explanation: Instead thin oxide capacitance over the gate area is used for calculation.

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