This set of VLSI test focuses on “Optimization of Inverters-2”.
1. Rise time and fall time can be also equalized by
a) Lp = Ln = λ
b) Lp = Ln = λ/2
c) Lp = Ln = 2λ
d) 2Lp = Ln = λ
Explanation: Rise time and fall time can be equalized by taking Lp = Ln = 2λ which implies Wp/Wn = 2 and also µn/µp = 2.
2. Equalizing of rise time and fall time is possible in
b) pseudo nMOS
Explanation: Equalizing of rise time and fall time is possible only in CMOS and not possible in nMOS and pseudo nMOS because of the ratio requirement.
3. High and low noise margins can be equalized by
a) βn = βp
b) βn greater than βp
c) βn lesser than βp
d) Lp = 2Ln
Explanation: High and low noise margins can be equalized by choosing βn = βp, also Ln = Lp which implies Wp/Wn = 2.
4. Inverter pair delay D is given as equal to
Explanation: Inverter pair delay D is given as the sum of rise time and fall time. This is proportional to (Rp+Rn)Cl where Rp and Rn are average resistances.
5. For minimum D consider
a) Ln = Lp = 2λ
b) Ln greater than Lp = 2λ
c) Lp greater than Ln
d) Lp = 2Ln
Explanation: D increases with Ln and Lp so for minimum D we have to choose Ln=Lp=2λ. D does not vary significantly with (1) lesser than (Wn/Wp) lesser than (2).
6. Different parameter optimization is easily achievable in
c) pseudo nMOS
Explanation: Different parameter optimizations like noise margins equalization, rise time fall time equalization can be easily achievable in CMOS.
7. Minimizing A with respect to Wp.d. gives
a) Wp.d. = 2λ
b) Wp.d. = λ/2
c) Wp.d. = (k)1/2 x 2λ
d) Wp.d. = k x (λ)1/2 x 2
Explanation: Minimizing A with respect to Wp.d yields a solution as Wp.d. = (k)1/2 x Wp.u. = (k)1/2 x 2λ.
8. Using Zp.u./Zp.d = k, Lp.u. can be obtained as
a) k x 2λ
b) k x λ
c) (k)1/2 x 2λ
d) k x 2 x (λ)1/2
Explanation: Using this ratio Zp.u./Zp.d. = k, we obtain Lp.u. = (k)1/2 x Lp.d. = (k)1/2 x 2λ.
9. Minimum area can be given as
a) 4 x Ao x λ x (k)1/2
b) 4 x Ao x λ x k
c) 8 x Ao x λ2 x (k)1/2
d) 8 x Ao x λ x (k)1/2
Explanation: Minimum area A can be given as 8 x Ao x λ2 x (k)1/2 which implies Zp.u. = (k)1/2 and Zp.d. = 1/(k)1/2.
10. When Zp.d. or Zp.u. increases, delay
c) remains the same
d) delay becomes zero
Explanation: Pd is minimized by increasing Zp.d.. Large Zp.d. requires large Zp.u. which results in increase in delay D of the inverter pair.
11. For minimum D which relation is choosen?
a) Zp.u. = 1/2k
b) Zp.u. = k
c) Zp.d. = 1/k
d) Zp.d. = 1
Explanation: For minimum D, Zp.u. is 1 and Zp.d. is equal to 1/k with Wp.u. = 2λ and Wp.d. = k x 2λ.
12. Noise margin measures the changing strength of
a) input voltage
b) output voltage
c) threshold voltage
d) supply voltage
Explanation: Noise margin measures by how much the input voltage can change without disturbing the present logic output state.
13. Which has better noise margins?
Explanation: CMOS has better noise margins than nMOS especially at low conditions because ratio adjustment is easier in CMOS.
Sanfoundry Global Education & Learning Series – VLSI.
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