This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Clocked Sequential Circuits”.
a) two phase overlapping clock
b) two phase non overlapping clock
c) four phase overlapping clock
d) four phase non overlapping clock
Explanation: Clocked sequential circuits are two phase non overlapping clock signal. Clock signals are distributed in two wires and it is non overlapping.
2. Which are easier to design?
a) clocked circuits
b) asynchronous sequential circuits
c) clocked circuits with buffer
d) asynchronous sequential circuits with buffers
Explanation: Clocked circuitry are easier to design than the asynchronous sequential circuits. But it is slower than the asynchronous sequential circuit.
3. _____ is used to drive high capacitance load
a) single polar capability
b) bipolar capability
c) tripolar capability
d) bi and tri polar capability
Explanation: Bipolar capability is used to drive high capacitance load. It can handle high loads as it is done by BiCMOS NAND gate logic.
4. As the temperature is increased, storage time ______
c) does not change
Explanation: As the temperature is increased, storage time is halved. It is inversely proportional to the storage time.
a) two, three
b) three, two
c) three, four
d) four, three
Explanation: Dynamic register element consists of three transistors for nMOS and four for CMOS.
6. Non inverting dynamic register storage cell consists of ____ transistors for nMOS and _____ for CMOS
a) six, eight
b) eight, six
c) five, six
d) six, five
Explanation: Non inverting dynamic register storage cell consists of six transistors for nMOS and eight for CMOS.
7. Register cell consists of
b) pass transistor
c) both of the mentioned
d) none of the mentioned
Explanation: Register cell consists of an inverter and a pass transistor or a transmission gate. Dynamic register cell consists of stick/circuit notation.
8. In a four bit dynamic shift register basic nMOS transistor or inverters are connected in
d) series and parallel
Explanation: The basic inverters or nMOS transistors are connected in cascade to obtain four bit dynamic shift register.
a) parallel output at inverters 1,3,5,7
b) parallel output at inverters 1,5,8
c) parallel output at all inverters
d) parallel output at inverter 2,4,6,8
Explanation: In four bit dynamic shift register , output is obtained parallely at inverters 2,4,6,8.
10. For signals which are updated frequently _____ is used
a) static storage
b) dymanic storage
c) static and dynamic storage
Explanation: For signals which are updated frequently dynamic storage elements are used. It can be done at < 0.25 msec interval.
Sanfoundry Global Education & Learning Series – VLSI.
To practice all areas of VLSI, here is complete set of 1000+ Multiple Choice Questions and Answers.