This set of VLSI Problems focuses on ” MESFET Design-2″.
1. In the ring diagram, green line is used to represent
a) E-MESFET
b) D-MESFET
c) Interconnection
d) Transistor
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Explanation: In the ring diagram, green or dotted line represents E-MESFET while yellow or solid line represents D-MESFET.
2. E-type and D-type is joined together using
a) metal 1
b) metal 2
c) vias
d) interconnectors
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Explanation: E-type and D-type features are joined together using blue color which represents metal 1 layer.
3. What is the intermediate stage in converting ring diagram to mask layout?
a) switch logic
b) transistor level diagram
c) symbolic diagram
d) stick diagram
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Explanation: The ring diagrams can be turned into mask layout directly or through an intermediate symbolic representation stage.
4. In symbolic representation, rings are converted into
a) color codes
b) switches
c) sticks
d) circuit elements
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Explanation: Symbolic representation is the intermediate stage when turning ring diagram to mask layout and here rings are represented as circuit elements.
5. For inverters color code used is
a) red followed by green paths
b) green followed by red paths
c) green followed by yellow paths
d) red followed by yellow paths
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Explanation: The green followed by yellow paths are drawn for inverters and inverter based logic such as NOR gates.
6. In symbolic representation _________ is used to represent E-MESFET.
a) red transistor
b) green transistor
c) yellow transistor
d) blue transistor
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Explanation: In symbolic representation, green transistor is used to represent E-MESFET and yellow transistor is used to represent D-MESFET.
7. Global control paths are run in
a) metal 2
b) metal 1
c) transistor
d) interconnects
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Explanation: Long signal and global control paths are run in metal 2 parallel with the power rails.
8. _______ gives the instruction for the preparation of photomasks.
a) design layout
b) design rules
c) color codes
d) layout map
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Explanation: Design rules are the prescription for the preparation of photomasks that are to be used in the fabrication of integrated circuits.
9. Design rule is not influenced by maturity of property line.
a) true
b) false
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Explanation: Design rules can also be influenced by maturity of the process line. If the process is mature, then one can be assured of the process line capability allowing tighter design with fewer constraints.
10. The separation between implant is determined from
a) width of transistor
b) width of E-MESFET
c) width of D-MESFET
d) width of photoresist
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Explanation: The separation between implant is determined from width of depletion region and width of photoresist.
11. MESFETs should be positioned
a) horizontally
b) vertically
c) diagonally
d) randomly
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Explanation: All MESFETs should be positioned horizontally owing to its anisotropic nature of GaAs which influences the threshold voltage of the device.
12. Saturated resistor is a
a) FET with schottky gate
b) FET without schottky gate
c) MESFET with schottky gate
d) MESFET without schottky gate
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Explanation: The saturated resistor is a MESFET with the schottky gate removed. The preferred direction for layout is vertical.
13. MIM capacitor uses
a) metal 1
b) metal 2
c) metal 1 and metal 2
d) schottky gate
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Explanation: The metal-insulator-metal (MIM) capacitor structure is simple using metal 1 and metal 2 as the plates of a parallel plate capacitor.
14. The mask is derived from the structural operation of masks.
a) true
b) false
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Explanation: The mask is derived from the logical operation of the active layer masks. Some processes require isolation between devices to reduce their interaction.
Sanfoundry Global Education & Learning Series – VLSI.
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