# VLSI Questions and Answers – Rules for Proper Design

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Rules for Proper Design”.

1. The Zp.u./Zp.d. ratio for nMOS inverter is
a) 4:1
b) 3:1
c) 1:4
d) 1:3

Explanation: For nMOS inverters the Zp.u./Zp.d. ratio is 4:1 when driven from another inverter and 8:1 when driven through one or more pass transistors.

2. The impedance ratio for pseudo-nMOS is
a) 4:1
b) 3:1
c) 1:4
d) 1:3

Explanation: For pseudo-nMOS, the Zp.u./Zp.d. ratio is 3:1 and for CMOS 1:1 ratio is required for minimum area.

3. What is the value for peripheral capacitance for 5 micron technology?
a) 4 x 10(-4) pf/µm2
b) 5 x 10(-4) pf/µm2
c) 8 x 10(-4) pf/µm2
d) 12 x 10(-4) pf/µm2

Explanation: Peripheral capacitance is the side wall capacitance. Peripheral capacitance of 5 micron technology is 8 x 10(-4) pf/µm2.

4. 1 square Cg is ___________ of MOS transistor.
a) gate to source capacitance
b) gate to drain capacitance
c) source to drain capacitance
d) gate to channel capacitance

Explanation: 1 square Cg is defined as the gate to channel capacitance of a MOS transistor having standard feature size (W=L).

5. What is the delay value Ʈ for 1.2 micron technology?
a) 0.1 nsec
b) 0.12 nsec
c) 0.046 nsec
d) 0.064 nsec

Explanation: The delay Ʈ is the time constant and for 1.2 micron technology its value is 0.046 nsec.
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6. Which is used to increase Ʈ?
a) parasitic capacitance
b) peripheral capacitance
c) area capacitance

Explanation: Circuit wiring and parasitic capacitance must be allowed to increase the value of Ʈ by the factor of 2 or 3.

7. The inverter pair delay is given by
a) (Zp.u./Zp.d.)Ʈ
b) (1+ Zp.u./Zp.d.)Ʈ
c) (1+ Zp.u./Zp.d.)Ʈ
d) (1+ Ʈ)Zp.u./Zp.d.

Explanation: The inverter delay is given by (1+ Zp.u./Zp.d.)Ʈ. The inverter pair delay for CMOS is 7Ʈ.

8. The number of stages N is given by
a) ln(y)/ln(f)
b) ln(f)/ln(y)
c) ln(2y)/ln(f)
d) ln(y)/ln(2f)

Explanation: To calculate the value for N, where N inverters are cascaded, each one of which is larger than the preceding stage by a width factor f the formula used is ln(y)/ln(f).

9. If f assumes the value e then delay is
a) maximized
b) minimized
c) does not change
d) doubled

Explanation: Total delay is minimized if f assumes the value of e which is the base of the natural logarithm. This applies to both nMOS and CMOS.

10. Propogation delay is given by
a) nrcƮ
b) n2rcƮ
c) nr2
d) n2

Explanation: Propogation delay through cascaded pass transistors or transmission gate can be given as n2rcƮ.

11. Using _____ long wires are possible.
a) silicide
b) metal
c) polysilicon
d) diffusion

Explanation: Using silicide, reasonable long wires are possible. It is a modest RC product. Silicides are used in place of polysilicon in some nMOS processes.

12. One pass transistor can be driven through output of another.
a) true
b) false

Explanation: No pass transistor gate must be driven through the output of one or more pass transistors since logic 1 levels are degraded by the threshold voltage.

13. Pass transistors are allowed to be constructed under
a) diffusion layer
b) polysilicon layer
c) metal layer
d) silicon layer

Explanation: Pass transistors are allowed to be constructed under metal layers to save space and is more convenient.

14. Maximum allowable current density in aluminium is
a) 0.1 mA/µm2
b) 0.5 mA/µm2
c) 2 mA/µm2
d) 1 mA/µm2

Explanation: The maximum allowable current density in aluminium wire is 1 mA/µm2. Otherwise metal migration may occur.

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