This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Gate Logic”.
1. Gate logic is also called as
a) transistor logic
b) switch logic
c) complementary logic
d) restoring logic
Explanation: Gate logic is also called as restoring logic. This is a logic circuitry designed so that even with an imperfect input pulse a standard output occurs at the exit of each successive logic gate.
2. Both NAND and NOR gates can be used in gate logic.
Explanation: Both NAND and NOR gates can be used in gate logic along with CMOS and AND and OR logic can be used in switch logic.
3. The CMOS inverter has _____ power dissipation
d) very less
Explanation: The CMOS inverter has no static current and no power dissipation. Static charge remains until it is able to move away by means of electric discharge.
4. As the number of inputs increases, the NAND gate delay
c) does not vary
d) exponentially decreases
Explanation: As the number of inputs increases, the NAND gate delay also increases because computation considering or using each input additional time is needed.
5. NAND gate delay can be given as
Explanation: NAND gate delay can be given as the product of number of inputs n and the nMOS inverter delay Ʈint.
6. In CMOS NAND gate, p transistors are connected in
Explanation: In CMOS NAND gate, p transistors are connected in parallel but once again the geometries may require thought when several inputs are required.
7. BiCMOS is used for ____ fan-out
d) very less
Explanation: BiCMOS NAND can be used when large fan-out is necessary. Fan-out is a term that defines the maximum number of digital inputs that the output of a single logic gate can feed.
8. Which can handle high capacitance load?
b) nMOS NAND
c) CMOS NAND
d) BiCMOS NAND
Explanation: BiCMOS NAND can handle high capacitance load. It is more complex and it can handle high capacitance load such as in the I/O region of a chip.
9. Which gate is faster?
Explanation: NOR gate is faster. NAND is more complex than NOR and thus NOR is faster and efficient.
10. For a pseudo nMOS design the impedance of pull up and pull down ratio is
Explanation: For a pseudo nMOS design, the ratio of Zp.u. and Zp.d. is 3:1.
Sanfoundry Global Education & Learning Series – VLSI.
To practice all areas of VLSI, here is complete set of 1000+ Multiple Choice Questions and Answers.