# VLSI Questions and Answers – Counters and Finite State Machines

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This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Counters and Finite State Machines”.

1. Counters detect only bridging faults.
a) true
b) false

Explanation: Counters detect gate level struck-at faults and bridging faults of the circuit under test.

2. How many test patterns are required to test the circuit using counters?
a) 2n
b) 2(n-1)
c) 2n – 1
d) 2n + 1

Explanation: A n-bit counter, generates 2 n possible test patterns which is sufficient to completely test n-bit combinational logic circuit with no feedback.

3. The desired N value for counters is
a) less than 50
b) less than 10
c) less than 25
d) less than 70

Explanation: The testing using counter method is practical for lesser value of N such as within 22 to 25 since for higher values of N more number of clock cycles are necessary.

4. The least significant bit toggles for
a) every clock cycle
b) every alternate clock cycle
c) every two clock cycles
d) every four clock cycles

Explanation: The least significant bit toggles every clock cycle and the most significant bit toggles every half way through and at the end of the count sequence.

5. Finite state machines are used for
a) deterministic test patterns
b) algorithmic test patterns
c) random test patterns
d) pseudo random test patterns

Explanation: Finite state machines are used for algorithmic test pattern generation testing for the circuit under test.

6. Address ordering minimizes the logic of finite state machines.
a) true
b) false

Explanation: Address ordering either ascending or descending order in the first and last loop minimizes the logic of finite state machines.

7. In finite state machine the data in and data out are
a) in same ports
b) different ports
c) same register
d) different register

Explanation: In finite state machine, there are separate ports for DATA IN and DATA OUT and this is a typical RAM structure.

8. _______ is used to control the read and write operations.
a) active low synchronous reset
b) active high synchronous reset
c) active low synchronous preset
d) active high synchronous preset

Explanation: With the use of active high synchronous reset (clear) read and write operations in a finite state machine can be done.

9. Finite state machine will initially set to all zeroes.
a) true
b) false

Explanation: Finite state machine has initial state initialized with all 0’s whereas LFSR and CA has initial state with any state other than all 0’s.

10. Fault coverage is ______ in finite state machines.
a) less
b) more
c) equal
d) none of the mentioned 