VLSI Questions and Answers – CMOS Logic Gates

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This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “CMOS Logic Gates”.

1. In negative logic convention, the Boolean Logic [1] is equivalent to:
a) +VDD
b) 0 V
c) -VDD
d) None of the mentioned
View Answer

Answer: b
Explanation: In negative logic convention, the Boolean Logic [1] is equivalent to 0 V and Logic ‘0’ is equivalent to +VDD.
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2. In positive logic convention, the true state is represented as:
a) 1
b) 0
c) -1
d) -0
View Answer

Answer: a
Explanation: In positive logic convention, the Boolean logic ‘1’ is known to be representing true state.

3. The CMOS gate circuit of NOT gate is:
a) vlsi-questions-answers-cmos-logic-gates-q3a
b) vlsi-questions-answers-cmos-logic-gates-q3b
c) vlsi-questions-answers-cmos-logic-gates-q3c
d) vlsi-questions-answers-cmos-logic-gates-q3d
View Answer

Answer: d
Explanation: The CMOS logic circuit for NOT gate has a p-MOS as a pull up transistor and n-MOS as driver transistor which is represented accurately in the below figurevlsi-questions-answers-cmos-logic-gates-q3d

4. The truth table which accurately explains the operation of CMOS not gate is:
a) vlsi-questions-answers-cmos-logic-gates-q4a
b) vlsi-questions-answers-cmos-logic-gates-q4b
c) vlsi-questions-answers-cmos-logic-gates-q4c
d) vlsi-questions-answers-cmos-logic-gates-q4d
View Answer

Answer: d
Explanation: The output of CMOS depends on the state of nMOS and pMOS transistor.The correct truth table is:vlsi-questions-answers-cmos-logic-gates-q4d

5. The CMOS logic circuit for NAND gate is:
a) vlsi-questions-answers-cmos-logic-gates-q5a
b) vlsi-questions-answers-cmos-logic-gates-q5b
c) vlsi-questions-answers-cmos-logic-gates-q5c
d) None of the mentioned
View Answer

Answer: a
Explanation: The accurate cmos logic circuit for NAND gate is:vlsi-questions-answers-cmos-logic-gates-q5a
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6. In CMOS logic circuit the n-MOS transistor acts as:
a) Load
b) Pull up network
c) Pull down network
d) Not used in CMOS circuits
View Answer

Answer: c
Explanation: A static CMOS gate has an nMOS pull-down network to connect the output to 0 (GND).

7. In CMOS logic circuit the p-MOS transistor acts as:
a) Pull down network
b) Pull up network
c) Load
d) Short to ground
View Answer

Answer: b
Explanation: A static CMOS gate has a pMOS pull-up network to connect the output to VDD (1).

8. In CMOS logic circuit, the switching operation occurs because:
a) Both n-MOSFET and p-MOSFET turns OFF simultaneously for input ‘0’ and turns ON simultaneously for input ‘1’
b) Both n-MOSFET and p-MOSFET turns ON simultaneously for input ‘0’ and turns OFF simultaneously for input ‘1’
c) N-MOSFET transistor turns ON, and p-MOSFET transistor turns OFF for input ‘1’ and N-MOS transistor turns OFF, and p-MOS transistor turns ON for input ‘0’
d) None of the mentioned
View Answer

Answer: c
Explanation: In CMOS logic circuit, the switching operation occurs because N-MOS transistor turns ON, and p-MOS transistor turns OFF for input ‘1’ and N-MOS transistor turns OFF, and p-MOS transistor turns ON for input ‘0’. The networks are arranged such that one is ON and the other OFF for any input pattern.

9. The CMOS logic circuit for NOR gate is:
a) vlsi-questions-answers-cmos-logic-gates-q9a
b) vlsi-questions-answers-cmos-logic-gates-q9b
c) vlsi-questions-answers-cmos-logic-gates-q9c
d) vlsi-questions-answers-cmos-logic-gates-q9d
View Answer

Answer: a
Explanation: vlsi-questions-answers-cmos-logic-gates-q9a
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10. When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is:
a) 1 or Vdd or HIGH state
b) 0 or ground or LOW state
c) High impedance or floating(Z)
d) None of the mentioned
View Answer

Answer: c
Explanation: When both pull up and pull down transistors are OFF, the high impedance for floating Z output state results.

11. When both nMOS and pMOS transistors of CMOS logic gates are ON, the output is:
a) 1 or Vdd or HIGH state
b) 0 or ground or LOW state
c) Crowbarred or Contention(X)
d) None of the mentioned
View Answer

Answer: c
Explanation: The crowbarred (or contention) X level exists when both pull up and pull down transistors are simultaneously turned ON. Contention between the two networks results in an indeterminate output level and dissipates static power.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn