VLSI Questions and Answers – CMOS Logics

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This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “CMOS Logics”.

1. In Pseudo-nMOS logic, n transistor operates in
a) cut off region
b) saturation region
c) resistive region
d) non saturation region
View Answer

Answer: b
Explanation: In Pseudo-nMOS logic, n transistor operates in saturation region and p transistor operates in resistive region.
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2. The power dissipation in Pseudo-nMOS is reduced to about ____ compared to nMOS device
a) 50%
b) 30%
c) 60%
d) 70%
View Answer

Answer: c
Explanation: The power dissipation in Pseudo-nMOS is reduced to about 60% compared to nMOS device.

3. Pseudo-nMOS has higher pull-up resistance than nMOS device.
a) true
b) false
View Answer

Answer: a
Explanation: Pseudo-nMOS has higher pull-up resistance than nMOS device and thus inverter pair delay is larger.

4. In dynamic CMOS logic _____ is used
a) two phase clock
b) three phase clock
c) one phase clock
d) four phase clock
View Answer

Answer: d
Explanation: In dynamic CMOS logic, four phase clock is used in which actual signals are used to derive the clocks.

5. In clocked CMOS logic, output in evaluated in
a) on period
b) off period
c) both periods
d) half of on period
View Answer

Answer: a
Explanation: In clocked CMOS logic, the logic is evaluated only in the on period of the clock. And owing to the extra transistor in series, slower rise time and fall times are expected.
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6. In clocked CMOS logic, rise time and fall time are
a) faster
b) slower
c) faster first and then slows down
d) slower first and then speeds up
View Answer

Answer: b
Explanation: In clocked CMOS logic, rise time and fall time are slower because of more number of transistors in series.

7. In CMOS domino logic _____ is used
a) two phase clock
b) three phase clock
c) one phase clock
d) four phase clock
View Answer

Answer: c
Explanation: In CMOS domino logic, single phase clock is used. Clock signals distributed on one wire is called as single or one phase clock.

8. CMOS domino logic is same as ______ with inverter at the output line
a) clocked CMOS logic
b) dynamic CMOS logic
c) gate logic
d) switch logic
View Answer

Answer: b
Explanation: CMOS domino logic is same as that of the dynamic CMOS logic with inverter at the output line.

9. CMOS domino logic occupies
a) smaller area
b) larger area
c) both of the mentioned
d) none of the mentioned
View Answer

Answer: a
Explanation: CMOS domino logic structure occupies smaller area than conventional CMOS logic as only n-block is used.

10. CMOS domino logic has
a) smaller parasitic capacitance
b) larger parasitic capacitance
c) low operating speed
d) very large parasitic capacitance
View Answer

Answer: a
Explanation: CMOS domino logic has smaller parasitic capacitance and higher operating speed.
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11. In CMOS domino logic _______ is possible
a) inverting structure
b) non inverting structure
c) inverting and non inverting structure
d) very complex design
View Answer

Answer: b
Explanation: In CMOS domino logic, only non inverting structures are possible because of the presence of the inverting buffer.

12. CMOS domino logic can be expressed diagramatically as
a) vlsi-questions-answers-cmos-logics-q12a
b) vlsi-questions-answers-cmos-logics-q12b
c) vlsi-questions-answers-cmos-logics-q12c
d)vlsi-questions-answers-cmos-logics-q12d
View Answer

Answer: a
Explanation: The correct form of CMOS domino logic representation is as given in the answer.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn