# VLSI Questions and Answers – Test and Testability

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Test and Testability “.

1. Circuit nodes cannot be probed for monitoring or excitation.
a) true
b) false

Explanation: The entire surface of the chip other than the pads are sealed by an overglass layers and thus circuit nodes cannot be probed for monitoring and excitation.

2. The circuit should be tested at
a) design level
b) chip level
c) transistor level
d) switch level

Explanation: Chip design mistakes can be very costly both in terms of time and money. The circuit should be tested at chip level itself. Design for testability is essential for good design.

3. ______ of the area is dedicated for testability.
a) 20%
b) 10%
c) 30%
d) 25%

Explanation: Design for testability is an essential process for good design. Thus the designers dedicate around 30% or more of chip area for testing.

4. Partitioning into subsystems are done at
a) design stage
b) prototype stage
c) testing stage
d) fabrication stage

Explanation: At the prototype stage, partitioning into subsystems are done to solve all the complexity problem. Each of these subsystems are self contained and independent.

5. In prototype testing, the circuits are
a) open circuited
b) short circuited
c) tested as a whole circuit
d) programmed

Explanation: The connections are made open circuited so that one system can be divorced from another as a last resort in prototype testing.

6. The number of test vectors for exhaustive testing is calculated by
a) 2(m+n)
b) 2((m+n)/2)
c) 2(m-n)
d) 22(m+n)

Explanation: The total number of test vectors for exhaustive testing is given by 2(m+n). For example if m is 20 and n is 24, the resultant number of test vectors for exhaustive testing is 244.

7. After partitioning, number of vectors is given by
a) 2(m+n)
b) 2((m+n)/2)
c) 2n+ 2m
d) 22(m+n)

Explanation: If the system is partitioned for testing, exhaustive testing can be reduced to 2n + 2m a much more reasonable proportion.

8. What are the dominant faults in diffusion layers?
a) short citcuit faults
b) open circuit faults
c) short and open circuit faults
d) power supply faults

Explanation: In MOS circuits, short circuit and open circuit in metal layer and short circuit in diffusion layer are the dominant fault experienced.

9. Test pattern generation is assisted using
a) automatic test pattern generator
b) exhaustive pattern generator
c) repeated pattern generator
d) loop pattern generator

Explanation: Test pattern generation is assisted using automatic test pattern generators but they are complicated to use properly and ATPG costs tend to rise rapidly with circuit size.

10. _____ of faults are easier to detect.
a) 50%
b) 60%
c) 70%
d) 80%

Explanation: It is relatively easy to detect the first 80% of faults using various classical test strategies.

11. Hot carrier injection causes
a) threshold voltage shift
c) threshold voltage shift & transconductance degradation
d) none of the mentioned

Explanation: Hot carrier injection causes both threshold voltage shift and transconductance degradation due to charge accumulation in the gate oxide.

12. Oxide breakdown occurs due to
a) electrostatic charge
b) threshold voltage
c) voltage shift

Explanation: Oxide breakdown occurs due to inadequate protection against electrostatic discharge and also due to defect or poor design in input/output pad circuitry.

13. Which model is used for pc board testing?
a) stuck at
b) stuck in
c) stuck on
d) stuck through

Explanation: The stuck at model is used in the testing of pc boards and is not sufficient to test actual VLSI CMOS circuits.

Sanfoundry Global Education & Learning Series – VLSI.

To practice all areas of VLSI, here is complete set of 1000+ Multiple Choice Questions and Answers.

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