# VLSI Questions and Answers – Test Pattern Generators

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Test Pattern Generators”.

1. The test pattern generator which uses a shift register along with LFSR is of __________ bits.
a) N
b) M
c) N+M
d) N*M

Explanation: The test pattern generator which uses a M-bit shift register with N-bit LFSR, the test pattern generator is of N+M bits.

2. The N+M bit test pattern generator has __________ different patterns produced.
a) 2(N+M)
b) 2N+M
c) 2NM
d) 2M+N

Explanation: The N+M bit test pattern generator can produce a maximum of 2N+M possible different patterns during its first cycle.

3. Which property can prevent high fault coverage?
a) fault limit
b) clock fault
d) linear dependencies

Explanation: The test pattern generated in this method will contain an additional property called linear dependencies that can prevent high fault coverage in some circuits.

4. __________ are used along with flip-flops to build accumulators.
b) multipliers
c) buffers
d) AND gates

Explanation: Adders can be used in conjunction with the flip-flops to construct an accumulator that functions in test pattern generators.

5. What is the desirable constant value to be used with the initial values?
a) 0
b) 1
c) N
d) M

Explanation: The constant value 1 can always be used with any initial value for a register to ensure that the accumulator increments through all combinations of test patterns.

6. Which can be used to check the working of accumulator?
b) shifter
c) multiplier
d) counter

Explanation: Counter would be more area efficient in testing whether accumulator increments through all combinations.

7. Test patterns produced by ________ have both high and least toggle rates.
a) random pattern generator
b) counters
c) LFSR
d) CA

Explanation: Test patterns generated by counters have least and high toogle rates of the least and most significant bits respectively.

8. Which method does not have carry out?
a) LFSR
b) CA
c) Counters
d) Random sequence generator

Explanation: The counter is a 8-bit binary up counter with active high count enable but with no carry out.

9. Which method is easiest to test?
a) LFSR
b) Counter
c) CA
d) Weighted LFSR

Explanation: LFSR method is the most area efficient method and is also the easiest method to test. This is its most important advantage.

10. Which requires more number of cycles for 100% fault coverage?
a) internal feedback LFSR
b) external feedback LFSR
c) weighted LFSR
d) ca

Explanation: External feedback LFSR takes more number of cycles for 100% fault coverage than internal feedback LFSR and CA methods.

11. The detectability profile can be determined using
a) D algorithm
b) Cellular automata
c) LFSR
d) Random testing

Explanation: The detectability of every fault in the circuit fault is needed for better testing. To determine this detectability profile, D algorithm is used which gives accurate results.

Sanfoundry Global Education & Learning Series – VLSI.

To practice all areas of VLSI, here is complete set of 1000+ Multiple Choice Questions and Answers.

If you find a mistake in question / option / answer, kindly take a screenshot and email to [email protected]