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VLSI Multiple Choice Questions | MCQs | Quiz

VLSI Interview Questions and Answers
Pratice VLSI questions and answers for interviews, campus placements, online tests, aptitude tests, quizzes and competitive exams.

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VLSI - Basic MOS Transistor-1
VLSI - Basic MOS Transistor-2
VLSI - Design
VLSI - NMOS Fabrication
VLSI - CMOS Fabrication
VLSI - BiCMOS Technology
VLSI - NMOS & CMOS
VLSI - Ids & Vds Relationships
VLSI - MOS Parameters
VLSI - NMOS Inverter
VLSI - CMOS Inverter
VLSI - NPN Bipolar Transistors
VLSI - BiCMOS Inverters
VLSI - CMOS Latch-Up
VLSI - BiCMOS Logic Gates
VLSI - Stick Diagram
VLSI - Design Rules & Layout1
VLSI - Design Rules & Layout2
VLSI - Sheet Resistance
VLSI - Area Capacitance
VLSI - Inverter Delays
VLSI - Drivers
VLSI - Propogation Delays
VLSI - Wiring Capacitances
VLSI - MOS Inverters
VLSI - MOS Capacitance
VLSI - Capacitive Loads
VLSI - Differential Amplifiers
VLSI - Single Stage Amplifiers
VLSI - Scaling Factors - 1
VLSI - Scaling Factors - 2
VLSI - Limitations of Scaling-1
VLSI - Limitations of Scaling-2
VLSI - MOS Circuits Scaling-1
VLSI - MOS Circuits Scaling-2
VLSI - Switch Logic
VLSI - Gate Logic
VLSI - CMOS Logics
VLSI - Sequential Circuits
VLSI - System Considerations
VLSI - CMOS Logic Gates
VLSI - Phase Locked Loops
VLSI - Design Processes
VLSI - ALU Subsystem Design
VLSI - Multiplier Systems
VLSI - Storage Elements - 1
VLSI - Storage Elements - 2
VLSI - Memory Cells
VLSI - Flash memory
VLSI - Inverters Optimization-1
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VLSI - Floor Layout
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VLSI - Proper Design Rules
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VLSI - CIF Code Design
VLSI - CAD Tools Design
VLSI - Simulators
VLSI - Test & Testability
VLSI - Combination Logic Test
VLSI - Sequential Logic Test
VLSI - Testability Guidelines-1
VLSI - Testability Guidelines-2
VLSI - Testability Guidelines-3
VLSI - Design Techniques-1
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VLSI - Self Built-In Test
VLSI - LFSR - 1
VLSI - LFSR - 2
VLSI - Cellular Automata
VLSI - Test Patterns
VLSI - Finite State Machines
VLSI - Pseudo-Random Test-1
VLSI - Pseudo-Random Test-2
VLSI - Pattern Generators Test
VLSI - Automatic Pattern Test
VLSI - Fault Models
VLSI - Testability Design
VLSI - Submicron CMOS
VLSI - Gallium Arsenide VLSI
VLSI - GA Doping Process - 1
VLSI - GA Doping Process - 2
VLSI - VLSI Structures - 1
VLSI - VLSI Structures - 2
VLSI - MESFET
VLSI - GaAs Fabrication - 1
VLSI - GaAs Fabrication - 2
VLSI - GaAs Fabrication - 3
VLSI - Device Modelling - 1
VLSI - Device Modelling - 2
VLSI - Transconductance
VLSI - FET Logic Inverter
VLSI - MESFET Design - 1
VLSI - MESFET Design - 2
VLSI - GaAs MESFET Logics
VLSI - FET
VLSI - MOS Transistor - 1
VLSI - MOS Transistor - 2
VLSI - NMOS & CMOS
VLSI - MOS Threshold Voltage
VLSI - Noise Margin
VLSI - MOS Device Noise

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VLSI Questions and Answers – Test Pattern Generators

Posted on May 24, 2017 by Manish

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Test Pattern Generators”.

1. The test pattern generator which uses a shift register along with LFSR is of _____ bits
a) N
b) M
c) N+M
d) N*M
View Answer

Answer: c
Explanation: The test pattern generator which uses a M-bit shift register with N-bit LFSR, the test pattern generator is of N+M bits.

2. The N+M bit test pattern generator has _____ different patterns produced
a) 2(N+M)
b) 2N+M
c) 2NM
d) 2M+N
View Answer

Answer: b
Explanation: The N+M bit test pattern generator can produce a maximum of 2N+M possible different patterns during its first cycle.

3. Which property can prevent high fault coverage?
a) fault limit
b) clock fault
c) linear interloading
d) linear dependencies
View Answer

Answer: d
Explanation: The test pattern generated in this method will contain an additional property called linear dependencies that can prevent high fault coverage in some circuits.

4. _____ are used along with flip-flops to build accumulators
a) adders
b) multipliers
c) buffers
d) AND gates
View Answer

Answer: a
Explanation: Adders can be used in conjunction with the flip-flops to construct an accumulator that functions in test pattern generators.

5. What is the desirable constant value to be used with the initial values?
a) 0
b) 1
c) N
d) M
View Answer

Answer: b
Explanation: The constant value 1 can always be used with any initial value for a register to ensure that the accumulator increments through all combinations of test patterns.

6. Which can be used to check the working of accumulator?
a) adder
b) shifter
c) multiplier
d) counter
View Answer

Answer: d
Explanation: Counter would be more area efficient in testing whether accumulator increments through all combinations.

7. Test patterns produced by ______ have both high and least toggle rates
a) random pattern generator
b) counters
c) LFSR
d) CA
View Answer

Answer: b
Explanation: Test patterns generated by counters have least and high toogle rates of the least and most significant bits respectively.

8. Which method does not have carry out?
a) LFSR
b) CA
c) Counters
d) Random sequence generator
View Answer

Answer: c
Explanation: The counter is a 8-bit binary up counter with active high count enable but with no carry out.

9. Which method is easiest to test?
a) LFSR
b) Counter
c) CA
d) Weighted LFSR
View Answer

Answer: a
Explanation: LFSR method is the most area efficient method and is also the easiest method to test. This is its most important advantage.

10. Which requires more number of cycles for 100% fault coverage?
a) internal feedback LFSR
b) external feedback LFSR
c) weighted LFSR
d) ca
View Answer

Answer: b
Explanation: External feedback LFSR takes more number of cycles for 100% fault coverage than internal feedback LFSR and CA methods.

11. The detectability profile can be determined using
a) D algorithm
b) Cellular automata
c) LFSR
d) Random testing
View Answer

Answer: a
Explanation: The detectability of every fault in the circuit fault is needed for a better testing. To determine this detectability profile, D algorithm is used which gives accurate results.

Sanfoundry Global Education & Learning Series – VLSI.
To practice all areas of VLSI, here is complete set of 1000+ Multiple Choice Questions and Answers.

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