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VLSI Multiple Choice Questions | MCQs | Quiz

VLSI Interview Questions and Answers
Practice VLSI questions and answers for interviews, campus placements, online tests, aptitude tests, quizzes and competitive exams.

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VLSI - Basic MOS Transistor-1
VLSI - Basic MOS Transistor-2
VLSI - Design
VLSI - NMOS Fabrication
VLSI - CMOS Fabrication
VLSI - BiCMOS Technology
VLSI - NMOS & CMOS
VLSI - Ids & Vds Relationships
VLSI - MOS Parameters
VLSI - NMOS Inverter
VLSI - CMOS Inverter
VLSI - NPN Bipolar Transistors
VLSI - BiCMOS Inverters
VLSI - CMOS Latch-Up
VLSI - BiCMOS Logic Gates
VLSI - Stick Diagram
VLSI - Design Rules & Layout1
VLSI - Design Rules & Layout2
VLSI - Sheet Resistance
VLSI - Area Capacitance
VLSI - Inverter Delays
VLSI - Drivers
VLSI - Propogation Delays
VLSI - Wiring Capacitances
VLSI - MOS Inverters
VLSI - MOS Capacitance
VLSI - Capacitive Loads
VLSI - Differential Amplifiers
VLSI - Single Stage Amplifiers
VLSI - Scaling Factors - 1
VLSI - Scaling Factors - 2
VLSI - Limitations of Scaling-1
VLSI - Limitations of Scaling-2
VLSI - MOS Circuits Scaling-1
VLSI - MOS Circuits Scaling-2
VLSI - Switch Logic
VLSI - Gate Logic
VLSI - CMOS Logics
VLSI - Sequential Circuits
VLSI - System Considerations
VLSI - CMOS Logic Gates
VLSI - Phase Locked Loops
VLSI - Design Processes
VLSI - ALU Subsystem Design
VLSI - Multiplier Systems
VLSI - Storage Elements - 1
VLSI - Storage Elements - 2
VLSI - Memory Cells
VLSI - Flash memory
VLSI - Inverters Optimization-1
VLSI - Inverters Optimization-2
VLSI - Floor Layout
VLSI - System Delays
VLSI - Proper Design Rules
VLSI - Design Styles
VLSI - CIF Code Design
VLSI - CAD Tools Design
VLSI - Simulators
VLSI - Test & Testability
VLSI - Combination Logic Test
VLSI - Sequential Logic Test
VLSI - Testability Guidelines-1
VLSI - Testability Guidelines-2
VLSI - Testability Guidelines-3
VLSI - Design Techniques-1
VLSI - Design Techniques-2
VLSI - Self Built-In Test
VLSI - LFSR - 1
VLSI - LFSR - 2
VLSI - Cellular Automata
VLSI - Test Patterns
VLSI - Finite State Machines
VLSI - Pseudo-Random Test-1
VLSI - Pseudo-Random Test-2
VLSI - Pattern Generators Test
VLSI - Automatic Pattern Test
VLSI - Fault Models
VLSI - Testability Design
VLSI - Submicron CMOS
VLSI - Gallium Arsenide VLSI
VLSI - GA Doping Process - 1
VLSI - GA Doping Process - 2
VLSI - VLSI Structures - 1
VLSI - VLSI Structures - 2
VLSI - MESFET
VLSI - GaAs Fabrication - 1
VLSI - GaAs Fabrication - 2
VLSI - GaAs Fabrication - 3
VLSI - Device Modelling - 1
VLSI - Device Modelling - 2
VLSI - Transconductance
VLSI - FET Logic Inverter
VLSI - MESFET Design - 1
VLSI - MESFET Design - 2
VLSI - GaAs MESFET Logics
VLSI - FET
VLSI - MOS Transistor - 1
VLSI - MOS Transistor - 2
VLSI - NMOS & CMOS
VLSI - MOS Threshold Voltage
VLSI - Noise Margin
VLSI - MOS Device Noise

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VLSI Questions and Answers – Floor Layout

Posted on May 24, 2017 by Manish

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Floor Layout”.

1. A 4-bit processor has two buses which are
a) unidirectional
b) bidirectional
c) one unidirectional and one bidirectional
d) more than two buses
View Answer

Answer: c
Explanation: A 4-bit processor has two buses one is bidirectional to carry operand and output to shifter and register array and another bus unidirectional to carry input.
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2. The IN and OUT bus lines relative positions are interchanged to
a) match height
b) match length
c) match width
d) match thickness
View Answer

Answer: a
Explanation: The IN and OUT bus line’s relative positions are interchanged to make the cell stretchable and to match the height of the block and spacings.

3. The IN and OUT bus lines should be in
a) metal
b) polysilicon
c) diffusion
d) silicon
View Answer

Answer: a
Explanation: The IN and OUT bus lines should be in metal rather than diffusion or polysilicon to mate with the bus structures of other blocks.

4. Extensions are
a) vertical
b) horizontal
c) diagonal
d) happazard
View Answer

Answer: b
Explanation: Extensions are horizontal or parallel to the stratified unit and rifts are described as extension zones.

5. Rifts and extensions should be placed in
a) minimum amount of geometry
b) maximum amount of geometry
c) in slopes
d) anywhere in the layout
View Answer

Answer: a
Explanation: Rifts and extensions should be placed where they cut a minimum amount of simple geometry, one in polysilicon and one in diffusion.
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6. Rifts are used for smooth flow through buses.
a) true
b) false
View Answer

Answer: a
Explanation: Rifts are used for smooth flow through buses as suggested and hence one in used in polysilicon and other in diffusion.

7. Input and output pads are made up of
a) polysilicon
b) metal
c) silicon
d) carbon
View Answer

Answer: b
Explanation: Input and output pads are made up of metal and it used to connect chips from one circuitry to another.

8. Bonding pads are placed
a) in the chip
b) exactly at the centre of chip
c) edge of the chip
d) above the chip
View Answer

Answer: c
Explanation: Bonding pads are positioned near to the edge of the chips although there will be a Vdd bus between bonding pads and chip boundary.

9. Which pad contains Schmitt trigger circuitry?
a) Vdd pads
b) Vss pads
c) input pads
d) output pads
View Answer

Answer: c
Explanation: Input pad contains over voltage protection features and also contains inverting circuitry or Schmitt trigger circuitry.

10. Which occupies lesser area?
a) Vdd pads
b) Vss pads
c) input pads
d) output pads
View Answer

Answer: d
Explanation: Output pads provide large current for off-wiring and also inputs to other devices. But these pads uses minimum space.

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11. Buffers are needed to drive
a) small capacitance
b) large capacitance
c) small resistance
d) large resistance
View Answer

Answer: b
Explanation: Buffers are necessary in environments on and off chip. It is used to drive relatively large capacitances associated with circuits off the chip.

12. Pads must be placed generally in the periphery of the chip area.
a) true
b) false
View Answer

Answer: a
Explanation: Usually pads must be placed in the periphery of the chip area otherwise bonding difficulties may be encountered.

13. How much area should be allocated for pads?
a) one third
b) two third
c) half
d) three fourth
View Answer

Answer: a
Explanation: According to a thumb rule, the small system designer should allow one third of the chip area for pads.

Sanfoundry Global Education & Learning Series – VLSI.
To practice all areas of VLSI, here is complete set of 1000+ Multiple Choice Questions and Answers.

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« Microwave Engineering Questions and Answers – Quadrature Hybrid
Microwave Engineering Questions and Answers – Lange Coupler »
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Deep Dive @ Sanfoundry:

  1. C# Programming Examples on LINQ
  2. Materials Science Questions and Answers
  3. VLSI Questions and Answers
  4. VLSI Questions and Answers – Test and Testability
  5. VLSI Questions and Answers – Stick Diagram
  6. VLSI Questions and Answers – Rules for Proper Design
  7. VLSI Questions and Answers – Guidelines for Testability -1
  8. VLSI Questions and Answers – nMOS and CMOS Fabrication
  9. VLSI Questions and Answers – nMOS Fabrication
  10. VLSI Questions and Answers – Sheet Resistance
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer and SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage & Cluster Administration, Advanced C Programming, SAN Storage Technologies, SCSI Internals and Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him below:
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