This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “FET Logic Inverter”.
1. Inverter uses D-MESFET as
b) switching device
Explanation: Direct-coupled FET logic inverter uses both depletion and enhancement type devices. E-MESFET is used as switching device and D-MESFET is used as load.
2. The allowable output voltage is limited by
a) load resistance
b) load capacitance
c) barreir height
d) material used for barrier
Explanation: The design of the inverter is similar to silicon nMOS circuitry and the allowable output voltage is limited by barreir height of the Schottky gate diode.
3. For depletion mode transistor, gate is connected to
Explanation: For the depletion mode transistor, the gate is connected to the source and it is always on and only the characterictic curve Vgs=0 is suitable.
4. In DCFL inverter, enhancement mode device is called as
a) pull down transistor
b) pull up transistor
Explanation: In direct-coupled FET logic inverter, depletion mode device is called the pull-up and enhancement mode device is called as pull-down transistor.
5. Maximum voltage across enhancement mode device corresponds to minimum voltage across depletion mode device.
Explanation: In direct-coupled FET logic inverter, maximum voltage across enhancement mode device corresponds to minimum voltage across the depletion mode transistor.
6. When current begins to flow, output voltage
c) remains constant
d) does not get affected
Explanation: When Vin exceeds threshold voltage, current begins to flow. Then the output voltage Vout decreses and the transistor becomes resistive.
7. Inverter threshold voltage is the point where
a) Vin = Vt
b) Vout = Vt
c) Vin = Vout
d) Vout lesser than Vin
Explanation: The point at which Vout = Vin, is denoted as Vinv. The transfer characterictic and Vinv can be shifted by variation of the ratio of pull-up to pull-down resistances.
8. For equal margin, Vinv is set as ______ of logic voltage swing
b) half of
c) one third
Explanation: Since the logic high level is limited by barreir potential then for equal margins Vinv is set to half of the logic voltage swing.
9. For E-MESFET, Vinv is set in midway between
a) Vdd and Vss
b) Vt and Vin
c) Vt and Vout
d) barrier potential and ground
Explanation: In pull-down device that is E-MESFET, the inverter threshold voltage Vinv is set midway between barrier potential and ground.
10. To improve packing density, gate length should be smaller.
Explanation: To improve packing density, gate length should be larger for the pull-up device. This will reduce drain to source saturation current.
11. The ratio of Zp.u./Zp.d. for E-MESFET is
Explanation: For E-MESFET, the Zp.u./Zp.d. ratio is 10/1. For MESFET with Lp.u.=Lp.d., Wp.u./Wp.d. is equal to 1/10.
12. In direct coupled logic, the input transistor base is connected to
a) base output
b) emitter output
c) collector output
Explanation: In direct coupled logic, the input transistor base is directly connected to the collector output without any base resistors.
13. Direct-coupled logic is easy to design.
Explanation: Direct-coupled logic devices have fewer components, are economical and simpler to design and fabricate.
14. For cascade inverters, the relation suitable is
a) Vin = Vout > Vinv
b) Vin = Vout = Vinv
c) Vin < Vout > Vinv
d) Vin > Vout = Vinv
Explanation: For cascade inverters without degradation of levels, the relatio suitable and required is Vin = Vout = Vinv.
Sanfoundry Global Education & Learning Series – VLSI.
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