This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Scan Design Techniques-1”.
1. The major difficulty in sequential circuit testing is in
a) determining output
b) determining internal state
c) determining external state
d) determining input combinations
View Answer
Explanation: The major difficulty in sequential circuit testing is in determining the internal state of the circuit.
2. The design technique helps in improving
a) controllability
b) observability
c) controllability and observability
d) overall performance
View Answer
Explanation: The design technique are directed at improving the controllability and observability of the internal states.
3. A sequential circuit contains combinational logic and storage elements in
a) feedback path
b) output node
c) input node
d) non feedback path
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Explanation: A sequential circuit contains combinational logic and storage elements in feedback path.
4. Storage elements in scan design technique is reconfigured to form
a) RAM
b) shift registers
c) buffers
d) amplifiers
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Explanation: Storage elements in the scan design technique is reconfigured to form a shift register known as the scan path.
5. Storage elements used are
a) D flipflops
b) JK flipflops
c) RS flipflops
d) All of the mentioned
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Explanation: Storage elements are usually D, JK and RS flipflop elements with the classical structure being modified by the addition of a two-way multiplexer on the data inputs.
6. The sequential circuit operates in _____ mode/modes of operation.
a) only one
b) two
c) three
d) four
View Answer
Explanation: The sequential circuit containing the scan paths has two modes of operation a normal and a test mode.
7. The efficiency of the test pattern generation is improved by
a) adding buffers
b) adding multipliers
c) partitioning
d) adding power dividers
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Explanation: The efficiency of the test pattern generation for the overall combinational logic circuit is improved by partitioning since its depth is reduced.
8. The scan path shift register is verified by
a) shifting in all zeroes first
b) shifting in all ones first
c) adding all ones
d) adding all zeroes
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Explanation: Before applying test patterns, the scan path shift register is verified by shifting all ones then all zeroes.
9. In level sensitive aspect, when an input change occurs, the response in
a) dependent of components
b) dependent on wiring delays
c) independent of wiring delays
d) independent of input combinations
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Explanation: In level sensitive aspect, when an input change occurs the response is independent of the component and wiring delays within the network.
10. In test mode, storage elements are connected as
a) parallel shift registers
b) serial shift register
c) combiners
d) buffers
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Explanation: In the test mode, storage elements are connected as a long serial shift register.
11. Which has more number of I/O pins?
a) lssd
b) partial scan
c) scan/set
d) random access scan
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Explanation: Random access scan method’s major disadvantage is that it has more number of I/O pins and no shift registers with flipflop are used.
12. Scan/set method has no interruption to normal operation.
a) true
b) false
View Answer
Explanation: Scan/set method has separate shift registers and has no interruption to normal operation.
13. Which method has high over head cost?
a) lssd
b) partial scan
c) scan/set
d) random access scan
View Answer
Explanation: Scan/set method has high overhead cost in terms of additional input/output pins.
Sanfoundry Global Education & Learning Series – VLSI.
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