This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “GaAs Fabrication -1”.
1. Gallium arsenide crystals are grown from
a) boron oxide
b) silicon oxide
c) silicon nitride
d) boron nitride
Explanation: Growth of gallium arsenide crystals from high purity boron nitride crubicles is becoming the primary growth technique.
2. Wafers in GaAs fabrication are thermally unstable.
Explanation: The fabrication of GaAs includes production of round wafers and they are thermally stable and have superior semi-insulating properties.
3. The sequence of the steps followed in fabrication of GaAs is
1. lapping 2. polishing 3. grinding 4. wafer scrubbing
Explanation: The steps followed in fabrication of GaAs are grinding the As-grown boules, wafering, edge rounding, lapping, polishing and then wafer scrubbing.
4. Which devices are fabricated using planar process?
a) enhancement mode MESFET
b) depletion mode MESFET
c) enhancement mode MOSFET
d) depletion mode MOSFET
Explanation: The depletion mode devices are fabricated using planar process where n-type dopants are directly implanted into semi-insulating GaAs.
5. Threshold voltage can be varied by
a) varying impurity concentration
b) varying doping level
c) varying channel length
d) varying source voltage
Explanation: Threshold voltage in GaAs can be varied by varying the channel thickness and the doping level of the active region.
6. Stable native oxide was produced by
a) oxidation of silicon
b) oxidation of gallium
c) oxidation of boron
d) oxidation of aluminium
Explanation: The driving force with siicon technology were brought about as the result of presence of stable native oxide which was readily produceded through oxidation of silicon.
7. In GaAs technology, deposited dielectric films brings about
Explanation: In GaAs technology, due to the absence of a stable native oxide deposited dielectric films brings about passivation or encapsulation.
8. Formation of n-active layer is achieved by
a) indirent ion implantation
b) direct ion implantation
Explanation: Formation of n-active layer is achieved by direct ion implantation into the GaAs semi-insulating substrate through the insulating layer.
9. Implantation of ________ is done for the formation of source and drain
a) n- layer
b) n+ layer
c) p- layer
d) p+ layer
Explanation: Implantation of a deep low resistivity n+ layer is done for the formation of source and drain and n-layer for formation of channel layer.
10. The channel resistance is high for
a) source contact
b) drain contact
c) gate contact
d) source and drain contacts
Explanation: The channel resistance is in the order of 1000 to 2500 ohm/square which is too high for source and drain contacts.
11. Stress at the interface cannot arise from
a) lattice mismatch
b) intrinsic stress
c) thermal mismatch
d) pressure mismatch
Explanation: Mechanical stability of thin film encapsulation layer depends upon stress at the interface and this can originate from lattice mismatch, intrinsic stress and thermal mismatch.
12. Which has the greatest mismatch?
Explanation: SiO2 has the greatest mismatch and its cofficient of thermal expansion is 0.5×10^(-6)/ degree celsius.
13. Which was employed as the first level capping material?
Explanation: Si3N4 has a dielectric constant of 7 compared to 3.9 for silicondioxide and silicondioxide was initially employed as the first-level capping material.
Sanfoundry Global Education & Learning Series – VLSI.
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