# VLSI Questions and Answers – Testing Sequential Logic

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Testing Sequential Logic”.

1. Sequential circuits are represented as
a) finite state machine
b) infinite state machine
c) finite synchronous circuit
d) infinite asynchronous circuit

Explanation: Sequential circuits are represented as finite state machine and may be modelled as combinational logic.

2. Sequential circuit includes
a) delays
b) feedback
c) delays and feedback from input to output
d) delays and feedback from output to input

Explanation: Sequential circuit includes a set of delays and feedback from output to input and it is known as finite state machine.

3. Which constitutes the test vectors in sequential circuits?
a) feedback variables
b) delay factors
c) test patterns
d) all input combinations

Explanation: The ‘m’ feedback variables constitute the state vector and determine the maximum number of finite states which may be assumed by the circuit.

4. Outputs are functions of
a) present state
b) previous state
c) next state
d) present and next state

Explanation: Next state and output are both functions of present state and the independent inputs.

5. Which is the delay elements for clocked system?
a) AND gates
b) OR gates
c) Flip-flops
d) Multiplexers

Explanation: In clocked systems, the basic delay elements are flip-flops and in asynchronous circuits, the delays may be contributed by circuit propagation delays.
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6. Which contributes to the necessary delay element?
a) flip-flops
b) circuit propagation elements
c) negative feedback path
d) shift registers

Explanation: The circuit propagation delays contribute to the necessary delay elements. The delay in the feedback path may be non-existence.

7. In an OR gate, if A and B are two inputs and there is struck at 1 fault in B path, then output will be
a) A
b) 0
c) 1
d) B’

Explanation: In an OR gate, if struck at 1 fault in present in B path then output will always be 1.

8. Iterative test generation method suits for circuits with
a) no feedback loops
b) few feedback loops
c) more feedback loops
d) negative feedback loops only

Explanation: The iterative test generation methods are best suited to logic with few feedback loops as in control logic for example.

9. Which method is very time consuming?
a) D-algorithm
b) iterative test generation
c) pseudo exhaustive method
d) test generation pattern

Explanation: Iterative test generation method is time consuming for circuits of any complexity. It is necessary to describe the initial states of the circuit, which is also time consuming.

10. In this technique, a simple fault manifests into multiple N faults.
a) true
b) false

Explanation: The main problem in this iterative test generation technique is that a simple fault in the sequential machine is manifest as N multiple faults during test.

11. In this iterative test generation method, sequential logic is
a) used in the same pattern
b) converted to test logic
c) converted to combinational logic
d) converted to asynchronous logic

Explanation: In this iterative test generation method, the main approach of testing is sequential logic is converted into combinational logic by cutting the feedback lines, thus creating pesudo inputs and outputs.

12. For a NAND gate, struck-at 1 fault in second input line cannot be detected if
a) Q is 1
b) Q is 0
c) Q changes from 1 to 0
d) Q changes from 0 to 1

Explanation: In a NAND gate, struck-at 1 fault in the second input line cannot be detected if the output Q is reset (Q=0) prior to applying the test sequence.

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