VLSI Questions and Answers – Scan Design Techniques-2

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This set of VLSI Multiple Choice Questions & Answers focuses on “Scan Design Techniques-2”.

1. The serial shift register is driven using
a) one over-lapping clock
b) two over-lapping clock
c) one non over-lapping clock
d) two non over-lapping clock
View Answer

Answer: d
Explanation: The serial shift register is driven using two non over-lapping clocks which can be controlled by primary inputs of the circuit.
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2. Which is used to control the scan path movement?
a) clock signals
b) input signals
c) output signals
d) delay signals
View Answer

Answer: a
Explanation: Two clock signals are used to control the scan path movements through the shift register latches.

3. The circuit operation is independent of
a) rise time
b) fall time
c) propogation delays
d) all of the mentioned
View Answer

Answer: d
Explanation: The circuit operation is independent of dynamic characteristics of the logic elements like rise time, fall time and propogation delays.

4. Which is not the function of LSSD method?
a) eliminates hazards
b) eliminates races
c) simplifies fault generation
d) stores the data
View Answer

Answer: d
Explanation: The advantages of LSSD are that it eliminates races and hazards, simplifies fault generation and fault simulation.

5. Boundary scan test is used to test
a) pins
b) multipliers
c) boards
d) wires
View Answer

Answer: c
Explanation: Boundary scan test involves scan path and self-testing to resolve the problems associated with boards carrying VLSI circuits.
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6. The boundary scan path is provided with
a) serial input pads
b) parallel input pads
c) parallel output pads
d) buffer pads
View Answer

Answer: a
Explanation: The boundary scan path is provided with serial input and output pads and with appropriate clock pads.

7. The boundary scan path tests the
a) input nodes
b) output nodes
c) buffer nodes
d) interconnection points
View Answer

Answer: d
Explanation: The boundary scan path test the interconnection between the various chips on the board.

8. Boundary scan method takes lesser time on test pattern generation.
a) true
b) false
View Answer

Answer: a
Explanation: Boundary scan method takes lesser time on test pattern generation and application.

9. The disadvantage of boundary scan method is that the fault coverage is less.
a) true
b) false
View Answer

Answer: b
Explanation: The boundary scan test method is simplified and efficient and also its fault coverage is increased.
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10. Which occupies lesser area?
a) lssd
b) boundary scan test
c) serial scan
d) partial scan
View Answer

Answer: d
Explanation: Partial scan is derived from scan path technique and it consumes very less area.

11. The partial scan approach scan
a) all input node faults
b) all output node faults
c) faults not detected by designer functional vector
d) all faults
View Answer

Answer: c
Explanation: The partial scan approach detects faults which are not detected by designer’s functional vectors.

12. In scan/set method, __________ is used to implement a scan path
a) serial registers
b) storage elements
c) parallel registers
d) separate register
View Answer

Answer: d
Explanation: In scan/set method, storage elements are not used to implement a scan path. A separate register is added to scan test data in and out.

Sanfoundry Global Education & Learning Series – VLSI.
To practice all areas of VLSI, here is complete set of 1000+ Multiple Choice Questions and Answers.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn