# VLSI Questions and Answers – MOS Circuits Area Capacitance and Delay Unit

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This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “MOS Circuits Area Capacitance and Delay Unit”.

1. Which of the following mainly constitutes the output node capacitance?
a) Inter electrode capacitance
b) Stray capacitance
c) Junction Parasitic capacitance
d) All of the mentioned

Explanation: Output node capacitance mainly consists of junction parasitic capacitance.

2. The junction parasitic capacitance are produced due to ____________
a) Source diffusion regions
b) Gate diffusion regions
c) Drain diffusion region
d) All of the mentioned

Explanation: The junction parasitic capacitance are produced due to drain diffusion capacitance.

3. The amount of parasitic capacitance at the output node is determined by __________
a) Concentration of the impurity doped
b) Size of the total drain diffusion area
c) Charges stored in the capacitor
d) None of the mentioned

Explanation: The amount of parasitic capacitance is a linear function of drain diffusion area.

4. The dominant component of the total output capacitance in submicron technology is?
a) Drain diffusion capacitance
b) Gate oxide capacitance
c) Interconnect capacitance
d) Junction parasitic capacitance

Explanation: Interconnect capacitance becomes dominant component in submicron technology.

5. Which of the following is dominant component in input capacitance?
a) Gate diffusion capacitance
b) Gate parasitic capacitance
c) Gate oxide capacitance
d) All of the mentioned

Explanation: For input capacitance, gate oxide capacitance is the main component.

6. The total load capacitance is calculated as the sum of __________
a) Drain capacitance in series with input capacitance
b) Drain capacitance + interconnect capacitance +input capacitance
c) Drain capacitance + interconnect capacitance – input capacitance
d) Drain capacitance in parallel with input capacitance

Explanation: Total load capacitance = Drain capacitance + interconnect capacitance +input capacitance.

7. The interconnect capacitance is formed by __________
a) Area between the interconnect lines
b) Interconnect lines between the gates
c) Inter electrode capacitance of interconnect lines
d) None of the mentioned

Explanation: Interconnect line between the gates form interconnect capacitance.

8. The amount of gate oxide capacitance is determined by __________
a) Charges present on the gate
b) Polarity of the gate
c) Charges present on the substrate
d) Area of the gate

Explanation: The amount of gate oxide capacitance is determined by the area of the gate.

9. By what amount is Sidewall doping larger than substrate doping concentration.
a) 5
b) 2
c) 1
d) 10

Explanation: The sidewall doping is 10 times larger.

10. Zero bias depletion capacitance per unit length at sidewall junctions is given by, (Cj is the zero bias depletion capacitance per unit area).
a) (√10).Cj.xj
b) (√5).Cj.xj
c) (√10).Cj.xj2
d) (√10).Cj.xj3

Explanation: Since the doping concentration is 10 times larger.

11. The typical value of capacitance in pF x 10-4/µm2 for gate to channel in λ based design is?
a) 1
b) 0.4
c) 0.2
d) 4

Explanation: The gate to channel capacitance in λ based design is 4 pF x 10-4/µm2.

12. The active capacitance is also called as __________
a) Parasitic capacitance
b) Interconnect capacitance
c) Junction capacitance
d) Diffusion capacitance

Explanation: Diffusion capacitance is also called as active capacitance.

13. The value of diffusion capacitance in pF x 10-4/µm2 in 2 µm design is?
a) 1.75
b) 4
c) 8
d) 16

Explanation: Diffusion capacitance has a value of 8 pF x 10-4/µm2.

14. The value of standard unit of capacitance is?
a) 0.01pF
b) 0.0032pF
c) 0.0023pF
d) All of the mentioned

Explanation: The value of standard unit of capacitance depends on the design style used.

15. The standard unit of capacitance is defined as?
a) Capacitance of gate to channel of MOS transistor having W = L dimensions
b) Capacitance of gate to channel of n-MOS transistor having W = 3L dimensions
c) Capacitance of gate to channel of p-MOS transistor having 3W = L dimensions
d) Capacitance of gate to channel of n-MOS transistor having W = L dimensions and p-MOS having W=3L dimensions 