# VLSI Questions and Answers – Pseudo-Random Test Patterns-1

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Pseudo-Random Test Patterns-1”.

1. Which exhibits low fault coverage?
a) random test pattern
b) pseudo random test pattern
c) deterministic test pattern
d) algorithmic test pattern

Explanation: The circuit under test exhibits low fault coverage when tested with pseudo random test generation method.

2. Large AND function will produce _______ infrequently.
a) logic 0
b) logic 0 and logic 1
c) logic 1
d) neither logic 0 or 1

Explanation: Large AND function produces logic 1 infrequently due to its equally likelihood of more 0’s whereas large OR function produces logic 0 infrequently.

3. The circuit which incorporates _______ can be tested with weighted pseudo-random test pattern.
a) preset
b) reset
c) clear
d) break

Explanation: The circuit under test which incorporates global reset or preset can be tested with pseudo-random test pattern method.

4. Circuits with global reset have fault coverage in the range of
a) 5% to 10%
b) 11% to 15%
c) 15% to 20%
d) 6% to 8%

Explanation: The circuit under test with global reset has fault coverage as low as 11% to 15% due to its fault detection blocking effect.

5. The probability of given bit in LFSR being logic 0 is
a) 0
b) 1
c) 0.25
d) 0.5

Explanation: The probability of given bit in LFSR being logic 0 is approximately 0.5 and NANDing two bits of LFSR gives probability as 0.25.
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6. Initialization of the test pattern generator to all 1’s generate
a) global reset
b) clear
c) toggle
d) buffer

Explanation: The initialization of the test pattern generator to all 1’s generates a global reset or preset during the first test vector for the initialization of circuit under test.

7. Reset signal weight is given as
a) 2m
b) 2(-m)
c) 2m
d) 2(-m)

Explanation: The rule of thumb is to make the reset signal weight as 2(-m) where m is chosen to be greater than the sequential depth of the circuit under test.

8. The sequential depth is the number of
a) OR gates
b) AND gates
c) flip flops
d) EX-OR gates

Explanation: The sequential depth of the circuit under test is the number of flip flops in the longest path between primary input and output.

9. AND gate is used to ensure whether the test patterns have sufficient clock cycles.
a) true
b) false

Explanation: NAND gate or NOR gate helps to ensure whether the test patterns have sufficient clock cycles to propagate through the circuit under test before reset occurs.

10. Which method has more area overhead?
a) random test pattern
b) pseudo random test pattern
c) algorithmic test pattern
d) deterministic test pattern

Explanation: The pseudo random test pattern method has more area overhead along with increased design time. These are the limitations of this method.

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