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VLSI Multiple Choice Questions | MCQs | Quiz

VLSI Interview Questions and Answers
Pratice VLSI questions and answers for interviews, campus placements, online tests, aptitude tests, quizzes and competitive exams.

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VLSI - Basic MOS Transistor-1
VLSI - Basic MOS Transistor-2
VLSI - Design
VLSI - NMOS Fabrication
VLSI - CMOS Fabrication
VLSI - BiCMOS Technology
VLSI - NMOS & CMOS
VLSI - Ids & Vds Relationships
VLSI - MOS Parameters
VLSI - NMOS Inverter
VLSI - CMOS Inverter
VLSI - NPN Bipolar Transistors
VLSI - BiCMOS Inverters
VLSI - CMOS Latch-Up
VLSI - BiCMOS Logic Gates
VLSI - Stick Diagram
VLSI - Design Rules & Layout1
VLSI - Design Rules & Layout2
VLSI - Sheet Resistance
VLSI - Area Capacitance
VLSI - Inverter Delays
VLSI - Drivers
VLSI - Propogation Delays
VLSI - Wiring Capacitances
VLSI - MOS Inverters
VLSI - MOS Capacitance
VLSI - Capacitive Loads
VLSI - Differential Amplifiers
VLSI - Single Stage Amplifiers
VLSI - Scaling Factors - 1
VLSI - Scaling Factors - 2
VLSI - Limitations of Scaling-1
VLSI - Limitations of Scaling-2
VLSI - MOS Circuits Scaling-1
VLSI - MOS Circuits Scaling-2
VLSI - Switch Logic
VLSI - Gate Logic
VLSI - CMOS Logics
VLSI - Sequential Circuits
VLSI - System Considerations
VLSI - CMOS Logic Gates
VLSI - Phase Locked Loops
VLSI - Design Processes
VLSI - ALU Subsystem Design
VLSI - Multiplier Systems
VLSI - Storage Elements - 1
VLSI - Storage Elements - 2
VLSI - Memory Cells
VLSI - Flash memory
VLSI - Inverters Optimization-1
VLSI - Inverters Optimization-2
VLSI - Floor Layout
VLSI - System Delays
VLSI - Proper Design Rules
VLSI - Design Styles
VLSI - CIF Code Design
VLSI - CAD Tools Design
VLSI - Simulators
VLSI - Test & Testability
VLSI - Combination Logic Test
VLSI - Sequential Logic Test
VLSI - Testability Guidelines-1
VLSI - Testability Guidelines-2
VLSI - Testability Guidelines-3
VLSI - Design Techniques-1
VLSI - Design Techniques-2
VLSI - Self Built-In Test
VLSI - LFSR - 1
VLSI - LFSR - 2
VLSI - Cellular Automata
VLSI - Test Patterns
VLSI - Finite State Machines
VLSI - Pseudo-Random Test-1
VLSI - Pseudo-Random Test-2
VLSI - Pattern Generators Test
VLSI - Automatic Pattern Test
VLSI - Fault Models
VLSI - Testability Design
VLSI - Submicron CMOS
VLSI - Gallium Arsenide VLSI
VLSI - GA Doping Process - 1
VLSI - GA Doping Process - 2
VLSI - VLSI Structures - 1
VLSI - VLSI Structures - 2
VLSI - MESFET
VLSI - GaAs Fabrication - 1
VLSI - GaAs Fabrication - 2
VLSI - GaAs Fabrication - 3
VLSI - Device Modelling - 1
VLSI - Device Modelling - 2
VLSI - Transconductance
VLSI - FET Logic Inverter
VLSI - MESFET Design - 1
VLSI - MESFET Design - 2
VLSI - GaAs MESFET Logics
VLSI - FET
VLSI - MOS Transistor - 1
VLSI - MOS Transistor - 2
VLSI - NMOS & CMOS
VLSI - MOS Threshold Voltage
VLSI - Noise Margin
VLSI - MOS Device Noise

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VLSI Questions and Answers – Pseudo-Random Test Patterns-1

Posted on May 24, 2017 by Manish

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Pseudo-Random Test Patterns-1”.

1. Which exhibits low fault coverage?
a) random test pattern
b) pseudo random test pattern
c) deterministic test pattern
d) algorithmic test pattern
View Answer

Answer: b
Explanation: The circuit under test exhibits low fault coverage when tested with pseudo random test generation method.

2. Large AND function will produce _______ infrequently
a) logic 0
b) logic 0 and logic 1
c) logic 1
d) neither logic 0 or 1
View Answer

Answer: c
Explanation: Large AND function produces logic 1 infrequently due to its equally likelihood of more 0’s whereas large OR function produces logic 0 infrequently.

3. The circuit which incorporates _______ can be tested with weighted pseudo-random test pattern
a) preset
b) reset
c) clear
d) break
View Answer

Answer: a
Explanation: The circuit under test which incorporates global reset or preset can be tested with pseudo-random test pattern method.

4. Circuits with global reset have fault coverage in the range of
a) 5% to 10%
b) 11% to 15%
c) 15% to 20%
d) 6% to 8%
View Answer

Answer: b
Explanation: The circuit under test with global reset has fault coverage as low as 11% to 15% due to its fault detection blocking effect.

5. The probability of given bit in LFSR being logic 0 is
a) 0
b) 1
c) 0.25
d) 0.5
View Answer

Answer: d
Explanation: The probability of given bit in LFSR being logic 0 is approximately 0.5 and NANDing two bits of LFSR gives probability as 0.25.

6. Initialization of the test pattern generator to all 1’s generate
a) golbal reset
b) clear
c) toggle
d) buffer
View Answer

Answer: a
Explanation: The initialization of the test pattern generator to all 1’s generates global reset or preset during the first test vector for initialization of circuit under test.

7. Reset signal weight is given as
a) 2m
b) 2(-m)
c) 2m
d) 2(-m)
View Answer

Answer: b
Explanation: The rule of thumb is to make the reset signal weight as 2(-m) where m is chosen to be greater than the sequential depth of the circuit under test.

8. The sequential depth is the number of
a) OR gates
b) AND gates
c) flip flops
d) EX-OR gates
View Answer

Answer: c
Explanation: The sequential depth of the circuit under test is the number of flip flops in the longest path between primary input and output.

9. AND gate is used to ensure whether the test patterns have sufficient clock cycles.
a) true
b) false
View Answer

Answer: b
Explanation: NAND gate or NOR gate helps to ensure whether the test patterns have sufficient clock cycles to propogate through the circuit under test before reset occurs.

10. Which method has more area overhead?
a) random test pattern
b) pseudo random test pattern
c) algorithmic test pattern
d) deterministic test pattern
View Answer

Answer: b
Explanation: The pseudo random test pattern method has more area overhead along with increased design time. These are the limitations of this method.

Sanfoundry Global Education & Learning Series – VLSI.
To practice all areas of VLSI, here is complete set of 1000+ Multiple Choice Questions and Answers.

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