This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Latch-up in CMOS”.
1. In latch-up condition, parasitic component gives rise to __________ conducting path
a) low resistance
b) high resistance
c) low capacitance
d) high capacitance
Explanation: In latch-up condition, parasitic component gives rise to low resistance conducting path between Vdd and Vss with disastrous results. Carefull control during fabrication is necessary to avoid this problem.
2. Latch-up can be induced by
a) incident radiation
b) reflected radiation
d) diffracted radiation
Explanation: Latch-up can be induced by glitches on the supply rail or by incident radiation.
3. How many transistors might bring up latch up effect in p-well structure?
Explanation: Two transistors and two resistances might bring up the latch-up effect in p-well structure. These are associated with p-well and with regions of the substrate.
4. Substrate doping level should be decreased to avoid the latch-up effect.
Explanation: An increase in substrate doping level with a consequent drop in the value of Rs can be used as a remedy for latch-up problem.
5. What can be introduced to reduce the latch-up effect?
a) latch-up rings
b) guard rings
c) latch guard rings
d) substrate rings
Explanation: The introduction of guard rings can reduce the effect of latch-up problem. Guard rings are diffusions which decouple the parasitic bipolar transistors.
6. Which process produces circuit which are less prone to latch-up effect?
Explanation: BiCMOS process produces circuits which are less likely to suffer from latch-up problems where as CMOS circuits are very highly prone to latch-up problems.
7. One of the factor in reducing the latch-up effect is
a) reduced p-well resistance
b) reduced n-well resistance
c) increased n-well resistance
d) increased p-well resistance
Explanation: One of the main factor in reducing the latch-up effect is reduced n-well resistance Rw. Reduction in Rw means that a larger lateral current is necessary to invite latch-up and higher value of holding current is also required.
8. The parasitic pnp transistor has the effect of _______ carrier lifetime
c) exponentially decreasing
d) exponentially increasing
Explanation: The parasitic pnp transistor has the effect of reducing carrier lifetime in the n-base region.
9. The reduction in carrier lifetime brings about
a) reduction in alpha
b) reduction in beta
c) reduction in current
d) reduction in voltage
Explanation: The parasitic pnp transistor has the effect of reducing carrier lifetime in the n-base region which results in radiation in beta.
10. To reduce latch-up effect substrate resistance should be high.
Explanation: To reduce the latch-up effect, substrate resistance Rs should be low. Reduction of Rs and Rw means that larger lateral current is necessary to invite latch-up.
11. Latch-up is the generation of
a) low impedance path
b) high impedance path
c) low resistance path
d) high resistance path
Explanation: Latch-up is the generation of low-impedance path in CMOS chips between the power suppply and ground rails.
12. Latch-up is brought about by BJTs
a) with positive feedback
b) with negative feedback
c) with no feedback
d) without BJT
Explanation: Latch-up occurs due to BJTs for a silicon-controlled rectifiers with positive feedback and virtually short circuit the power and ground rail.
13. Sudden transient in power can cause latch-up.
Explanation: Sudden transient in power and ground buses are also among the reason which causes latch-up effect.
14. BJT gain should be ______ to avoid latch-up effect
c) should be maintained constant
d) changed randomly
Explanation: BJT gain should be reduced by lowering the minority carrier lifetime through doping of the substrate to lower the latch-up effect.
Sanfoundry Global Education & Learning Series – VLSI.
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