VLSI Questions and Answers – Fault Models

«
»

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Fault Models “.

1. Which are processing faults?
a) missing contact window
b) parasitic transistor
c) oxide breakdown
d) all of the mentioned
View Answer

Answer: d
Explanation: Some of the real defects in chip such as processing faults are missing contact window, parasitic transistor and oxide breakdown.
advertisement

2. Surface impurities occurs due to ion migration.
a) true
b) false
View Answer

Answer: a
Explanation: Some of the material defects are bulk defects and surface impurities. Bulk defects are cracks and crystal imperfection and surface impurities occurs due to ion migration.

3. Electromigration is a
a) processing fault
b) material defects
c) time dependent failure
d) packaging fault
View Answer

Answer: c
Explanation: Different types of real defects in chips are processing fault, material defects, time dependent failure and packaging fault. Time dependent failures are dielectric breakdown and electromigration.

4. Which relation is correct?
a) failure – error – fault
b) fault – error – failure
c) error – fault – failure
d) error – failure – fault
View Answer

Answer: b
Explanation: The relation fault – error – failure is correct. Error is caused by faults and failure which is a deviation of the circuit is caused by error.

5. For a circuit with k lines, ____ single stuckat fault is possible
a) k
b) 2k
c) k/2
d) k2
View Answer

Answer: b
Explanation: For a circuit with k lines, 2k single stuck-at faults are possible and 3^k – 1 multiple stuck-at faults are possible.
advertisement

6. Single stuck-at fault is technology independent.
a) true
b) false
View Answer

Answer: a
Explanation: Single stuck-at fault is technology independent. It can be applied to TTL, CMOS etc. It is also design style independent.

7. For a n signal lines circuit, ______ bridging faults are possible
a) n
b) 2n
c) n2
d) n/2
View Answer

Answer: c
Explanation: For circuit with n lines, n2 bridging faults are possible. Bridging fault occurs when two lines are connected when they should not be connected. It leads to wired AND or wired OR.

8. IDDQ fault occurs when there is
a) increased voltage
b) increased quiescent current
c) increased power supply
d) increased discharge
View Answer

Answer: b
Explanation: When input is low, both P and N transistors are conducting causing increase in quiescent current which leads to IDDQ fault.

9. Which fault causes output floating?
a) stuck-open
b) stuck-at
c) stuck-on
d) IDDQ
View Answer

Answer: a
Explanation: Transistor with stuck-open fault causes output floating. Stuck-open faults requires two vector tests.
advertisement

10. Data retention time comes under _____ fault
a) functional fault
b) memory fault
c) parametric fault
d) structural fault
View Answer

Answer: c
Explanation: One of the memory faults is parametric fault. Some of the parametric faults are noise margin, data retention time, power consumption, output levels etc.

11. In PLA, missing cross point in OR-array leads to
a) OR fault
b) growth fault
c) missing fault
d) disapperance fault
View Answer

Answer: d
Explanation: In PLA, missing cross point in AND array leads to growth fault and missing cross point in OR-array leads to disapperance fault.

12. In PLA, extra crosspoint in AND-array leads to
a) OR fault
b) growth fault
c) missing fault
d) disapperance fault
View Answer

Answer: d
Explanation: In PLA, extra crosspoint in AND-array leads to shrinkage or disapperance fault whereas extra crosspoint in OR-array leads to appearance fault.

13. The number of paths ______ with number of gates
a) increases exponentially
b) decreases exponentially
c) remains the same
d) increases rapidly
View Answer

Answer: a
Explanation: The number of paths increases exponentially with number of gates. Propogation delay of the path exceeds the clock interval.
advertisement

14. The quality of the test set is measured by
a) fault margin
b) fault detection
c) fault correction
d) fault coverage
View Answer

Answer: d
Explanation: The quality of a test set is measured by its fault coverage. It gives the fraction of fault that are detected by the test set.

Sanfoundry Global Education & Learning Series – VLSI.
To practice all areas of VLSI, here is complete set of 1000+ Multiple Choice Questions and Answers.

advertisement
advertisement
advertisement
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn