This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Guidelines for Testability -1”.
1. Practical guidelines for testability aims at
a) facilitating test generation
b) facilitating test application
c) avoiding timing problems
d) all of the mentioned
View Answer
Explanation: Practical guidelines for testability should aim to facilitate test process in three main ways – facilitate test generation, facilitate test application and avoid timing problems.
2. When a node is difficult to access
a) sub nodes are formed
b) internal pads are added
c) external pads are added
d) circuit is sub divided
View Answer
Explanation: When a node is difficult to access from primary input or output pads, then a very effective method is to add additional internal pads to access the desired point.
3. The additional pads are accessed using
a) probers
b) selectors
c) multiplexers
d) buffers
View Answer
Explanation: The additional pads which are added for the access of nodes, can be accessed using probers.
4. Which provides links between blocks of a circuit?
a) combiners
b) wires
c) pads
d) nodes
View Answer
Explanation: A node provides the link between blocks of a circuit and the attributes provide the control of the blocks.
5. To improve controllability and observability ______ is used.
a) three pads
b) eight transistors
c) three pads and eight transistors
d) four pads and eight transistors
View Answer
Explanation: In CMOS environment, three pads and eight transistors are required to improve controllability and observability.
6. The addition of ______ improves the observability.
a) adders
b) multiplexers
c) multipliers
d) demultiplexers
View Answer
Explanation: The addition of demultiplexers also improves observability. This arrangement allows bypassing of blocks.
7. How to reduce test time?
a) by reducing multiplexers
b) by reducing adders
c) by dividing circuit into subcircuits
d) by using the whole circuit as a single system
View Answer
Explanation: Partitioning large circuits into smaller subcircuits is an effective way of reducing test generation complexity and test time.
8. Test generation effort for n gate circuit is proportional to
a) n
b) n2
c) n3
d) n2 and n3
View Answer
Explanation: Test generation effort for a n gate general purpose logic circuit is proportional to n2 and n3.
9. Patitioning should be made on a
a) logical basis
b) functional basis
c) time basis
d) structural basis
View Answer
Explanation: Partitioning should be made on logical basis into recognizable and sensible subfunctions and can be done physically by incorporating clock line isolation and power supply lines.
10. Isolation and control is achieved using
a) adders
b) buffers
c) multiplexers
d) multipliers
View Answer
Explanation: Isolation and control are better and readily achieved through the use of multiplexers.
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