# VLSI Questions and Answers – Testing Combinational Logic

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Testing Combinational Logic”.

1. The input signal combination in exhaustive testing is given as
a) 2N
b) 21/N
c) 2(M+N)
d) 1/2N

Explanation: For testing an N input circuit using exhaustive testing, the total number of input combinations can be given as 2N.

2. Observability is the process of
a) checking all inputs
b) checking all outputs
c) checking all possible inputs
d) checking errors and performance

Explanation: Observability is the process of observing outputs for all the input combinations.

3. Exhaustive testing is suitable when N is
a) small
b) large
c) any value for N
d) very large

Explanation: Exhaustive testing is the process where all possible input combinations are used. This is suitable when N is relatively small.

4. Test vectors in sensitized path-based testing is generated
a) before enumerating faults
b) after enumerating faults
c) after designing
d) before designing

Explanation: In sensitized path-based testing, test vectors are generated after enumerating the possible faults because many patterns may not occur during the application of the circuit.

5. To propagate the fault along the selected path to primary output, setting _____ is done.
a) AND to 1
b) OR to 1
c) NOR to 1
d) NAND to 0

Explanation: Inputs of another gate is determined so as to propagate the fault signal along the selected path to primary output of the circuit. This is done by setting AND/NAND to 1 and OR/NOR to 0.

6. In consistency/ justification, tracking is done
a) forward from gate input to primary input
b) backwards from gate input to primary output
c) backwards from gate input to primary input
d) forward from gate output to primary output

Explanation: Consistency step finds the input patterns to realize all the necessary values. This is done by tracking backwards from gate input to primary input of the logic.

7. In D-algorithm, a particular ______ fault is detected by examining the _____ conditions.
a) internal, output
b) internal, input
c) external, output
d) external, input

Explanation: In a circuit comprising combinational logic, D-algorithm aims at detecting a particular internal fault by examining the output conditions.

8. D-algorithm is based on
a) existence of one fault machine
b) existence of one good machine
c) existence of one fault and one good machine
d) existence of two fault machines alone

Explanation: D-algorithm is based on the hypothesis of the existence of two machines – one good machine and one faulty machine.

9. The existence of fault in faulty machine causes discrepancy in behaviour of the circuit for all values on inputs.
a) true
b) false

Explanation: The existence of fault in faulty machine causes discrepancy in its behaviour and that of the good machine for some particular values of inputs.

10. In D-algorithm, the discrepancy is driven to _____ and observed and thus detected.
a) all inputs
b) particular inputs
c) output
d) end of the circuit

Explanation: In D-algorithm, a systematic means is provided to driven the discrepancy to output and it is observed and detected.

11. D-algorithm is time intensive for large circuits.
a) true
b) false

Explanation: D-algorithm is extremely time intensive and computing intensive for large circuits and many modifications and improvements are done.

Sanfoundry Global Education & Learning Series – VLSI.

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