This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Drivers”.
1. For shorter delays ______ resistance should be used
a) smaller
b) larger
c) does not depend on resistance
d) very large
View Answer
Explanation: For shorter delays low resistance should be used as delay is directly proportional or related to resistance.
2. To reduce resistance value of inverters, channels must be made
a) wider
b) narrower
c) lenghthier
d) shorter
View Answer
Explanation: Channels must be made wider to reduce the resistance value that is low resistance values for Zp.u. ad Zp.d. imply low L:W ratios and thus consequently an inverter to meet this need occupies a larger area.
3. As width increases, capacitive load
a) increases
b) decreases
c) does not change
d) exponentially increases
View Answer
Explanation: As width of the channel increases, capacitive load also increases and with this the area occupied also increases. The rate at which the width increases affects the stages N and load capacitance.
4. Delay per stage for logic 0 to 1 transition can be given as
a) fƮ
b) 2fƮ
c) 3fƮ
d) 4fƮ
View Answer
Explanation: Delay per stage for logic 0 to 1 transition can be given as fƮ. With large f, N decreases but delay per stage increases.
5. Delay per stage for logic 1 to 0 transition can be given as
a) fƮ
b) 2fƮ
c) 3fƮ
d) 4fƮ
View Answer
Explanation: Delay per stage for logic 1 to 0 transition can be given as 4fƮ. Using the delay for transition from 1 to 0 and 0 to 1 total nMOS delay can be obtained.
6. Total delay of an nMOS pair is
a) fƮ
b) 2fƮ
c) 5fƮ
d) 4fƮ
View Answer
Explanation: Total delay of an nMOS pair is equal to 5fƮ. This can be calculated by knowing delay per stage, that is for two different transitions from 0 to 1 and vice versa.
7. Total delay of an CMOS pair is
a) 5fƮ
b) 7fƮ
c) 8fƮ
d) 4fƮ
View Answer
Explanation: Total delay of an CMOS pair is equal to 7fƮ. This can be calculated by knowing thee delay per stage of CMOS.
8. The number of stages N can be given as
a) ln(y)*ln(f)
b) ln(y)/ln(f)
c) ln(f)/ln(y)
d) ln(f)/ln(2y)
View Answer
Explanation: The number of stages N can be given as ln(y)/ln(f). By knowing whether the number of stages N is even or odd we can calculate the total delay for nMOS, CMOS etc.
9. When number of stages N is even, the total delay for nMOS can be given as
a) 1.5NfƮ
b) 2.5NfƮ
c) 3.5NfƮ
d) 4.5NfƮ
View Answer
Explanation: When number of stages N is even, the total delay for nMOS can be given as 2.5NfƮ. This is calculated by using the formula (N/2)*5fƮ.
10. When number of stages N is even, the total delay for CMOS can be given as
a) 1.5NfƮ
b) 2.5NfƮ
c) 3.5NfƮ
d) 4.5NfƮ
View Answer
Explanation: When number of stages N is even, the total delay for CMOS can be given as 3.5NfƮ. This is calculated by using the formula (N/2)*7fƮ.
11. In BiCMOS drivers, the input voltage Vbe is _______ on base width
a) directly proportional
b) inversely proportional
c) logarithmically proportional
d) exponentially proportional
View Answer
Explanation: In BiCMOS driver, the input voltage Vbe is logarithmically proportional to the base width Wb and on electron mobility.
12. Which has larger value?
a) Tin
b) TL
c) Rc
d) None of the mentioned
View Answer
Explanation: In BiCMOS drivers, the initial time Tin necessary to charge base emitter junction is larger than the time TL requires to charge the output load capacitance.
13. In BiCMOS driver, a good bipolar transistor should have
a) low Rc
b) high hfe
c) high gm
d) all of the mentioned
View Answer
Explanation: In BiCMOS drivers, a good bipolar transistor should have low Rc, high hfe, high gm etc.
Sanfoundry Global Education & Learning Series – VLSI.
To practice all areas of VLSI, here is complete set of 1000+ Multiple Choice Questions and Answers.
