VLSI Questions and Answers – System Delays

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This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “System Delays”.

1. Which provides large capacitance?
a) load capacitance
b) bus wiring capacitance
c) sheet capacitance
d) area capacitance
View Answer

Answer: b
Explanation: Bus wiring capacitance Cbus provides the largest capacitance for a typical bus system for example for small chips this can be as high as 0.8pF.
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2. Bus wiring capacitance is driven through
a) one transistor
b) two transistors
c) three transistors
d) no transistors
View Answer

Answer: a
Explanation: Bus wiring capacitance is driven through pull-up and pull-down transistors and through atleast one pass transistor or transmission gate in the series.

3. What is the delay of input pads?
a) 5Ʈ
b) 10Ʈ
c) 40Ʈ
d) 30Ʈ
View Answer

Answer: d
Explanation: Input pad always contains over voltage protection circuitry and Schmitt trigger circuitry. Its total delay is 30Ʈ.

4. The total delay for the select register circuit is
a) 33Ʈ
b) 60Ʈ
c) 55Ʈ
d) 73Ʈ
View Answer

Answer: d
Explanation: The total delay for the select register is 73Ʈ. It is the sum of delays of input pad, three pass transistors and driver inverter pair.

5. Delay for data propagation is
a) 10 nsec
b) 50 nsec
c) 100 nsec
d) 150 nsec
View Answer

Answer: c
Explanation: Data is propagated through bus. Bus can be bidirectional but at data can be propagated through bus only at one direction at a time. The delay for this data propagation is 100nsec.
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6. Which is the longest delay in adder process?
a) sum delay
b) carry delay
c) propagation delay
d) inverter delay
View Answer

Answer: b
Explanation: The longest delay in the adder process is the carry chain delay. This is the process of forming carry out which propagates through all bits of the adder.

7. The total delay for the adder process is
a) 100 nsec
b) 200 nsec
c) 220 nsec
d) 250 nsec
View Answer

Answer: c
Explanation: The total delay for the adder process is 220 nsec. The total delay is the sum of select register delay, bus delays and carry chain delays.

8. The refreshing clock period should propagate through
a) memory cell
b) wiring
c) carry chain
d) any sub unit
View Answer

Answer: b
Explanation: The clock 2 which is the refreshing clock should propagate through wiring and finite rise and fall time must be allowed.

9. The value of Ʈ for 5 micron technology is always constant.
a) true
b) false
View Answer

Answer: b
Explanation: The range of value of Ʈ for 5 micron technology was calculated to be 0.1 to 0.3 nsec but it may vary upto 0.6 nsec.
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10. The total clock period for adder process is
a) 100 nsec
b) 150 nsec
c) 200 nsec
d) 250 nsec
View Answer

Answer: d
Explanation: The total clock period of the adder process is 250 nsec which is the sum of all the delay (220 nsec) and the period of different phases of the process.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn