# VLSI Questions and Answers – Optimization of Inverters-1

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Optimization of Inverters-1”.

1. Reduction in power dissipation can be brought by
a) increasing transistor area
b) decreasing transistor area
c) increasing transistor feature size
d) decreasing transistor feature size

Explanation: The 3:1 reduction in power dissipation can be brought at the expense of increasing the transistor area by 50%.

2. When does the longest delay occur in 8:1 inverters?
a) during 1 to 0 transition
b) during 0 to 1 transition
c) during faster speed
d) delays are always short

Explanation: In 8:1 inverters, the longest delay will occur when the output of the first stage is changing from logic 0 to 1 and capacitance must charge through pull-up resistance.

3. In inverter during logic 1 to 0 transition, capacitance discharges at
a) pull-up resistance
b) pull-down resistance
c) both pull-up and pull-down
d) at gate

Explanation: During the logic 1 to 0 transition, the capacitance which is charged through pull-up must always discharge through pull-down transistor at first stage.

4. In minimum size nMOS 8:1 inverter, the logic 0 to 1 transition delay is given as
a) 5Ʈ
b) 20Ʈ
c) 40Ʈ
d) 50Ʈ

Explanation: For minimum pull-down feature size nMOS 8:1 inverter, the logic 0 to 1 transition delay can be given as 8Rs x 5 square Cg which gives 40Ʈ.

5. In minimum size nMOS 8:1 inverter, the logic 1 to 0 transition delay is given as
a) 5Ʈ
b) 20Ʈ
c) 40Ʈ
d) 50Ʈ

Explanation: 8:1 nMOS inverter allows stray and wiring capacitance and the logic 1 to 0 transition delay can be given as 1Rs x 5 square Cg which gives 5Ʈ.
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6. For a regular 8:1 inverter, the transition delay is given as
a) 10Ʈ
b) 20Ʈ
c) 21Ʈ
d) 25Ʈ

Explanation: For 8:1 inverter the logic 0 to 1 transition delay can be given as 21Ʈ and logic 1 to 0 transition delay can be given as 2(1/3)Ʈ.

7. The area of CMOS inverter is proportional to
a) area of n device
b) area of p device
c) total area of n and p device
d) square of minimum feature size

Explanation: The area of a basic CMOS inverter is proportional to the total area occupied bu the p and n devices (WpLp + WnLn).

8. The ratio of Wp/Wn can be given as
a) 1:2
b) 2:1
c) 1:1
d) 2:2

Explanation: Minimum area can be achieved by choosing minimum dimensions for Wp, Wn, Lp, Ln which is 2λ and the ratio of Wp/Wn can be given as 1:1.

9. Switching power dissipation can be given as
a) Cl x Vdd x f
b) Vdd2 x f
c) Cl x Vdd2
d) Cl x Vdd2 x f

Explanation: Switching power dissipation Psd can be given as Cl x Vdd2 x f where Cl is load capacitance, Vdd is power supply voltage and f is the frequency of switching.

10. Load capacitance can be minimized by
a) increasing A
b) decreasing A
c) increasing Psd
d) does not depend on A

Explanation: For fixed Vdd and f, minimizing Psd requires minimizing Cl which can be minimized by decreasing area A as it is directly proportional to gate area.

11. Rise time and fall time can be equalized by
a) βn = βp
b) βn = 2βp
c) βp = 2βn
d) βn = 1/2βp

Explanation: Rise time tr and fall time tf can be equalized by using βn = βp, which requires (Wp/Lp) = (µn/µp)(Wn/Ln).

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