Logic Design Questions and Answers – Modeling Combinational Logic Using VHDL Processes

This set of Sequential Logic Design Multiple Choice Questions & Answers (MCQs) focuses on “Modeling Combinational Logic Using VHDL Processes”.

1. Write a synthesizable VHDL architecture using a VHDL process for the given VHDL entity of a 4:1 multiplexer. Assume that the IEEE library and std_logic_1164 package of IEEE library are included. The output of the multiplexer is active HIGH.

entity mux is 
port(I : in std_logic_vector(3 downto 0);
    A, B: in std_logic;
    F : out std_logic);
end;

a)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
    case (sel) is
    when "00" => F <= I(0);
    when "01" => F <= I(1);
    when "10" => F <= I(2);
    when "11" => F <= I(3);
    when others => null;
    end case;
end process;
end architecture comb_process;

b)

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architecture comb_process of mux is
begin
sel <= A&B;
process(all)
begin
    case (sel) is
    when "00" => F <= I(0);
    when "01" => F <= I(1);
    when "10" => F <= I(2);
    when "11" => F <= I(3);
    when others => null;
    end case;
end process;
end architecture comb_process;

c)

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architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
    case (sel) is
    when "00" => F <= I(3);
    when "01" => F <= I(2);
    when "10" => F <= I(1);
    when "11" => F <= I(0);
    when others => null;
    end case;
end process;
end architecture comb_process;

d)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
    case (sel) is
    when "11" => F <= I(0);
    when "10" => F <= I(1);
    when "01" => F <= I(2);
    when "00" => F <= I(3);
    end case;
end process;
end architecture comb_process;
View Answer
Answer: a
Explanation:
This is the truth table of a 4:1 multiplexer.

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A B F
0 0 I(0)
0 1 I(1)
1 0 I(2)
1 1 I(3)

Based on this table the VHDL code is written.



2. Write a synthesizable VHDL architecture using a VHDL process for the given VHDL entity of a quadruple 2:1 multiplexer. Assume that the IEEE library and std_logic_1164 package of IEEE library are included. If the control input A is 0, the output gets the value of X; if the control input A is 1, the output gets the value of Y. The output of the multiplexer is active HIGH.

entity mux is 
port(X, Y : in std_logic_vector(3 downto 0);
    A: in std_logic;
    F: out std_logic_vector(3 downto 0));
end;

a)

architecture comb_process of mux is
begin
process(all)
begin
    case (A) is
    when '0' => F <= X;
    when '1' => F <= Y;
    when others => null;
    end case;
end process;
end architecture comb_process;

b)

architecture comb_process of mux is
begin
process(all)
begin
    case (A) is
    when '1' => F <= X;
    when '0' => F <= Y;
    when others => null;
    end case;
end process;
end architecture comb_process;

c)

architecture comb_process of mux is
begin
process(all)
begin
    case (A) is
    when '0' => F <= Y;
    when '1' => F <= X;
    when others => null;
    end case;
end architecture comb_process;

d)

architecture comb_process of mux is
process(all)
begin
    case (A) is
    when '0' => F <= X;
    when '1' => F <= Y;
    when others => null;
    end case;
end process;
end architecture comb_process;
View Answer
Answer: a
Explanation:
This is the truth table of a quadruple 2:1 multiplexer.

A F
0 X
1 Y

Based on this table the VHDL code is written.



3. Write a synthesizable VHDL architecture using a VHDL process for the given VHDL entity of a 4:1 multiplexer. Assume that the IEEE library and std_logic_1164 package of IEEE library are included. The output of the multiplexer is active LOW.

entity mux is 
port(I   : in std_logic_vector(3 downto 0);
    A, B: in std_logic;
    F   : out std_logic);
end;

a)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
    case (sel) is
    when "00" => F <= I(0);
    when "01" => F <= I(1);
    when "10" => F <= I(2);
    when "11" => F <= I(3);
    when others => null;
    end case;
end process;
end architecture comb_process;

b)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
signal y: std_logic;
begin
sel <= A&B;
process(all)
begin
    case (sel) is
    when "00" => y <= I(0);
    when "01" => y <= I(1);
    when "10" => y <= I(2);
    when "11" => y <= I(3);
    when others => null;
    end case;
F <= not y;
end process;
end architecture comb_process;

c)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
signal y: std_logic;
begin
sel <= A&B;
process(all)
begin
    case (sel) is
    when "00" => y <= I(0);
    when "01" => y <= I(1);
    when "10" => y <= I(2);
    when "11" => y <= I(3);
    when others => null;
    end case;
F <= y;
end process;
end architecture comb_process;

d)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
    case (sel) is
    when "11" => F <= I(0);
    when "10" => F <= I(1);
    when "01" => F <= I(2);
    when "00" => F <= I(3);
    end case;
end process;
end architecture comb_process;
View Answer
Answer: b
Explanation:
This is the truth table of a 4:1 multiplexer. The output is active LOW.

A B F
0 0 not I(0)
0 1 not I(1)
1 0 not I(2)
1 1 not I(3)

Based on this table the VHDL code is written.



4. Write a synthesizable VHDL architecture using a VHDL process for the given VHDL entity of a 4:1 multiplexer with an Enable input. Assume that the IEEE library and std_logic_1164 package of IEEE library are included. The output of the multiplexer is active HIGH. The Enable input is active HIGH.

entity mux is 
port(I   : in std_logic_vector(3 downto 0);
    A, B, enable: in std_logic;
    F   : out std_logic);
end;

a)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
    if enable = '0' then
        F <= '0';
    else   
        case (sel) is
        when "00" => F <= I(0);
        when "01" => F <= I(1);
        when "10" => F <= I(2);
        when "11" => F <= I(3);
        when others => null;
        end case;
    end if;   
end process;
end architecture comb_process;

b)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
    if enable = '1' then
        F <= '0';
    else   
        case (sel) is
        when "00" => F <= I(0);
        when "01" => F <= I(1);
        when "10" => F <= I(2);
        when "11" => F <= I(3);
        when others => null;
        end case;
    end if;   
end process;
end architecture comb_process;

c)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
    if enable == '0' 
        F <= '0';
    else  begin 
        case (sel) is
        when "00" => F <= I(0);
        when "01" => F <= I(1);
        when "10" => F <= I(2);
        when "11" => F <= I(3);
        when others => null;
        end case;
    end if;   
end process;
end architecture comb_process;

d)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
process(all)
begin
    if enable = '0' 
        F <= '0';
    else   
        case (sel) is
        when "00" => F <= I(0);
        when "01" => F <= I(1);
        when "10" => F <= I(2);
        when "11" => F <= I(3);
        when others => null;
        end case;
    end if;   
end process;
end architecture comb_process;
View Answer
Answer: a
Explanation:
This is the truth table of a 4:1 multiplexer with an active HIGH enable input.

Enable A B F
0 X X 0
1 0 0 I(0)
1 0 1 I(1)
1 1 0 I(2)
1 1 1 I(3)

Based on this table the VHDL code is written.



5. Write a synthesizable VHDL architecture using a VHDL process for the given VHDL entity of a 4:1 multiplexer with an Enable input. Assume that the IEEE library and std_logic_1164 package of IEEE library are included. The output of the multiplexer is active HIGH. The Enable input is active LOW.

entity mux is 
port(I   : in std_logic_vector(3 downto 0);
    A, B, enable: in std_logic;
    F   : out std_logic);
end;

a)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
    if enable = '0' then
        F <= '0';
    else   
        case (sel) is
        when "00" => F <= I(0);
        when "01" => F <= I(1);
        when "10" => F <= I(2);
        when "11" => F <= I(3);
        when others => null;
        end case;
   end if;   
end process;
end architecture comb_process;

b)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
    if enable = '1' then
        F <= '0';
    else   
        case (sel) is
        when "00" => F <= I(0);
        when "01" => F <= I(1);
        when "10" => F <= I(2);
        when "11" => F <= I(3);
        when others => null;
        end case;
    end if;   
end process;
end architecture comb_process;

c)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
    if enable == '0' 
        F <= '0';
    else  begin 
        case (sel) is
        when "00" => F <= I(0);
        when "01" => F <= I(1);
        when "10" => F <= I(2);
        when "11" => F <= I(3);
        when others => null;
        end case;
    end if;   
end process;
end architecture comb_process;

d)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
process(all)
begin
    if enable = '0' 
        F <= '0';
    else   
        case (sel) is
        when "00" => F <= I(0);
        when "01" => F <= I(1);
        when "10" => F <= I(2);
        when "11" => F <= I(3);
        when others => null;
        end case;
   end if;   
end process;
end architecture comb_process;
View Answer
Answer: b
Explanation:
This is the truth table of a 4:1 multiplexer with an active LOW enable input.

Enable A B F
1 X X 0
0 0 0 I(0)
0 0 1 I(1)
0 1 0 I(2)
0 1 1 I(3)

Based on this table the VHDL code is written.



6. Write a synthesizable VHDL architecture using a VHDL process for the given VHDL entity of a 4:1 multiplexer with an Enable input. Assume that the IEEE library and std_logic_1164 package of IEEE library are included. The output of the multiplexer is active LOW. The Enable input is active HIGH.

entity mux is 
port(I   : in std_logic_vector(3 downto 0);
    A, B, enable: in std_logic;
    F   : out std_logic);
end;

a)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
signal y: std_logic;
begin
sel <= A&B;
process(all)
begin
if enable = '0' then
    F <= '0';
else 
    case (sel) is
    when "00" => y <= I(0);
    when "01" => y <= I(1);
    when "10" => y <= I(2);
    when "11" => y <= I(3);
    when others => null;
    end case;
F <= not y;
end if;
end process;
end architecture comb_process;

b)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
signal y: std_logic;
begin
sel <= A&B;
process(all)
begin
if enable = '1' then
    F <= '0';
else 
    case (sel) is
    when "00" => y <= I(0);
    when "01" => y <= I(1);
    when "10" => y <= I(2);
    when "11" => y <= I(3);
    when others => null;
    end case;
F <= not y;
end if;
end process;
end architecture comb_process;

c)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
signal y: std_logic;
begin
sel <= A&B;
process(all)
begin
    case (sel) is
    when "00" => y <= I(0);
    when "01" => y <= I(1);
    when "10" => y <= I(2);
    when "11" => y <= I(3);
    when others => null;
    end case;
F <= not y;
end process;
end architecture comb_process;

d)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
if enable = '1' then
    F <= '0';
else   
    case (sel) is
    when "00" => F <= I(0);
    when "01" => F <= I(1);
    when "10" => F <= I(2);
    when "11" => F <= I(3);
    when others => null;
    end case;
end if;   
end process;
end architecture comb_process;
View Answer
Answer: a
Explanation:
This is the truth table of a 4:1 multiplexer with an enable input. The output is active LOW. The enable input is active HIGH.

Enable A B F
0 X X 0
1 0 0 not I(0)
1 0 1 not I(1)
1 1 0 not I(2)
1 1 1 not I(3)

Based on this table the VHDL code is written.



7. Write a synthesizable VHDL architecture using a VHDL process for the given VHDL entity of a 4:1 multiplexer with an Enable input. Assume that the IEEE library and std_logic_1164 package of IEEE library are included. The output of the multiplexer is active LOW. The Enable input is active LOW.

entity mux is 
port(I   : in std_logic_vector(3 downto 0);
    A, B, enable: in std_logic;
    F   : out std_logic);
end;

a)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
signal y: std_logic;
begin
sel <= A&B;
process(all)
begin
if enable = '0' then
    F <= '0';
else 
    case (sel) is
    when "00" => y <= I(0);
    when "01" => y <= I(1);
    when "10" => y <= I(2);
    when "11" => y <= I(3);
    when others => null;
    end case;
F <= not y;
end if;
end process;
end architecture comb_process;

b)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
signal y: std_logic;
begin
sel <= A&B;
process(all)
begin
if enable = '1' then
    F <= '0';
else 
    case (sel) is
    when "00" => y <= I(0);
    when "01" => y <= I(1);
    when "10" => y <= I(2);
    when "11" => y <= I(3);
    when others => null;
    end case;
F <= not y;
end if;
end process;
end architecture comb_process;

c)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
signal y: std_logic;
begin
sel <= A&B;
process(all)
begin
    case (sel) is
    when "00" => y <= I(0);
    when "01" => y <= I(1);
    when "10" => y <= I(2);
    when "11" => y <= I(3);
    when others => null;
    end case;
F <= not y;
end process;
end architecture comb_process;

d)

architecture comb_process of mux is
signal sel: std_logic_vector(1 downto 0);
begin
sel <= A&B;
process(all)
begin
if enable = '1' then
    F <= '0';
else   
    case (sel) is
    when "00" => F <= I(0);
    when "01" => F <= I(1);
    when "10" => F <= I(2);
    when "11" => F <= I(3);
    when others => null;
    end case;
end if;   
end process;
end architecture comb_process;
View Answer
Answer: b
Explanation:
This is the truth table of a 4:1 multiplexer with an enable input. The output is active LOW. The enable input is active LOW.

Enable A B F
1 X X 0
0 0 0 not I(0)
0 0 1 not I(1)
0 1 0 not I(2)
0 1 1 not I(3)

Based on this table the VHDL code is written.



8. Write a synthesizable VHDL architecture using a VHDL process for the given VHDL entity of a 2:4 decoder with an Enable input. The Enable input is active HIGH. Assume that the IEEE library and std_logic_1164 package of IEEE library are included.

entity decoder is 
port(A, B, enable: in std_logic;
    F  : out std_logic_vector(3 downto 0));
end;

a)

architecture comb_process of decoder is 
signal s: std_logic_vector(1 downto 0);
begin
s <= A&B;
process(all)
begin
if enable = '0' then
    F <= "0000";
else 
    case (s) is 
    when "00" => F <= "0001";
    when "01" => F <= "0010";
    when "10" => F <= "0100";
    when "11" => F <= "1000";
    when others => null;
    end case;
end if;
end process;
end architecture;

b)

architecture comb_process of decoder is 
signal s: std_logic_vector(1 downto 0);
begin
s <= A&B;
process(all)
begin
if enable = '1' then
    F <= "0000";
else 
    case (s) is 
    when "00" => F <= "0001";
    when "01" => F <= "0010";
    when "10" => F <= "0100";
    when "11" => F <= "1000";
    when others => null;
    end case;
end if;
end process;
end architecture;

c)

architecture comb_process of decoder is 
signal s: std_logic_vector(1 downto 0);
begin
s <= A&B;
process(all)
begin
if enable = '0' then
    F <= "0000";
else 
    case (s) is 
    when "00" => F <= "1000";
    when "01" => F <= "0100";
    when "10" => F <= "0010";
    when "11" => F <= "0001";
    when others => null;
    end case;
end if;
end process;
end architecture;

d)

architecture comb_process of decoder is 
signal s: std_logic_vector(1 downto 0);
begin
s <= A&B;
process(all)
begin
if enable = '1' then
    F <= "0000";
else 
    case (s) is 
    when "00" => F <= "1000";
    when "01" => F <= "0100";
    when "10" => F <= "0010";
    when "11" => F <= "0001";
    when others => null;
    end case;
end if;
end process;
end architecture;
View Answer
Answer: a
Explanation:
This is the truth table of a 2:4 decoder with Enable input. The enable input is active HIGH.

Enable A B F0 F1 F2 F3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

Based on this table the VHDL code is written.



9. Write a synthesizable VHDL architecture using a VHDL process for the given VHDL entity of a 2:4 decoder with an Enable input. The Enable input is active LOW. Assume that the IEEE library and std_logic_1164 package of IEEE library are included.

entity decoder is 
port(A, B, enable: in std_logic;
    F  : out std_logic_vector(3 downto 0));
end;

a)

architecture comb_process of decoder is 
signal s: std_logic_vector(1 downto 0);
begin
s <= A&B;
process(all)
begin
if enable = '0' then
    F <= "0000";
else 
    case (s) is 
    when "00" => F <= "0001";
    when "01" => F <= "0010";
    when "10" => F <= "0100";
    when "11" => F <= "1000";
    when others => null;
    end case;
end if;
end process;
end architecture;

b)

architecture comb_process of decoder is 
signal s: std_logic_vector(1 downto 0);
begin
s <= A&B;
process(all)
begin
if enable = '1' then
    F <= "0000";
else 
    case (s) is 
    when "00" => F <= "0001";
    when "01" => F <= "0010";
    when "10" => F <= "0100";
    when "11" => F <= "1000";
    when others => null;
    end case;
end if;
end process;
end architecture;

c)

architecture comb_process of decoder is 
signal s: std_logic_vector(1 downto 0);
begin
s <= A&B;
process(all)
begin
if enable = '0' then
    F <= "0000";
else 
    case (s) is 
    when "00" => F <= "1000";
    when "01" => F <= "0100";
    when "10" => F <= "0010";
    when "11" => F <= "0001";
    when others => null;
    end case;
end if;
end process;
end architecture;

d)

architecture comb_process of decoder is 
signal s: std_logic_vector(1 downto 0);
begin
s <= A&B;
process(all)
begin
if enable = '1' then
    F <= "0000";
else 
    case (s) is 
    when "00" => F <= "1000";
    when "01" => F <= "0100";
    when "10" => F <= "0010";
    when "11" => F <= "0001";
    when others => null;
    end case;
end if;
end process;
end architecture;
View Answer
Answer: b
Explanation:
This is the truth table of a 2:4 decoder with Enable input. The enable input is active LOW.

Enable A B F0 F1 F2 F3
1 X X 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 1 0 0
0 1 0 0 0 1 0
0 1 1 0 0 0 1

Based on this table the VHDL code is written.


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