Logic Design Questions and Answers – Simulation and Testing of Sequential Circuits

This set of Logic Design Multiple Choice Questions & Answers (MCQs) focuses on “Simulation and Testing of Sequential Circuits”.

1. Which one of the following best describes “simulation” for sequential circuits?
a) Creating a PCB layout of the circuit
b) Designing the circuit on software only
c) Designing and observe the working of the circuit by virtually running it
d) Writing a VHDL code for the circuit
View Answer

Answer: c
Explanation: Simulation of a digital system can take place at several levels of detail. Simulation is a process by which a circuit is created virtually, run and the working is observed. This “simulation” step is very much required as we must be aware of the working and efficiency of the circuit.

2. Which one of the following is a possible result of simulation of sequential circuits?
a) Digital bits
b) Graphs
c) Timing diagrams
d) Current and voltages
View Answer

Answer: c
Explanation: Simulation of a digital system can take place at several levels of detail. Simulation is a process by which a circuit is created virtually, run and the working is observed. For the simulation of a sequential circuit, the simulator output usually includes timing diagrams which show the times at which different signals in the circuit change.

3. What is a “unit delay model”?
a) A model where the total propagation delay is unit
b) A model where the propagation delay of every element is assumed as unity
c) A model where there is no propagation delay
d) A model where there is 2 units of propagation delay totally
View Answer

Answer: b
Explanation: The delays in the gates and flip-flops may be modelled in several ways. The simplest method is to assume that each element has one unit of delay. Such a model is called as a “unity delay model” where the propagation delay of every element is assumed as unity.
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4. Which one of the following is not a part of testing of sequential circuits?
a) Observation of the outputs
b) Verification of state tables
c) Defining voltage levels at input or output
d) Using the direct set and clear inputs, set the flip-flop states to correspond to one of the present states in the table
View Answer

Answer: c
Explanation: Testing of sequential circuits is generally more difficult than testing combinational circuits. If the flip-flop outputs can be observed, then the state table can be verified directly on a row-by-row basis. But defining the voltage levels is not an operation to be done during testing. It should be defined earlier.

5. How are the state transition graphs presented during simulation and testing?
a) Using triangular pulse
b) Using sine pulse
c) Using rectangular pulse
d) Using spikes
View Answer

Answer: c
Explanation: In a states transition graph, the input and the output signals can be graphed. Several on and off conditions are represented here. Rectangular pulses are used for this purpose. Presence of a pulse signifies digital 1 and absence signifies logic 0.

6. Which one of the following is the main purpose of event-driven simulation?
a) To eliminate unnecessary gate simulations without introducing an unacceptable amount of additional testing
b) To get the count of errors occurred during simulation
c) To set a blueprint of the logic circuit
d) To get the count of logic gates used inside the circuitry
View Answer

Answer: a
Explanation: The process of event-Driven Simulation is built to eliminate unnecessary gate simulations without introducing an unacceptable amount of additional testing. An event is defined to be a change in the value of a net.

Sanfoundry Global Education & Learning Series – Logic Design.

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To practice all areas of Logic Design, here is complete set of 1000+ Multiple Choice Questions and Answers.

If you find a mistake in question / option / answer, kindly take a screenshot and email to [email protected]

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Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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