# Logic Design Questions and Answers – Equivalent Sequential Circuits

This set of Logic Design Multiple Choice Questions & Answers (MCQs) focuses on “Equivalent Sequential Circuits”.

1. When two sequential circuits are considered as “equivalent”?
a) If same components are used
b) If they perform same “work”
c) If both have same number of components
d) Both are absolutely same looking

Explanation: Sequential circuits are circuits where the output depends on present output as well as previous outputs. Essentially, two sequential circuits are equivalent if they are capable of doing the same “work.” We also need a memory to store the previous values.

2. How can an equivalent sequential circuit be formed?
a) By eliminating one or more elements
b) By reducing the number of equivalent states in the state table
b) By reducing number of transmission lines as wish
d) By using fewer number of gates

Explanation: Reducing the number of rows usually leads to a sequential circuit with fewer gates and flip-flops. So, reduction of equivalent states is a very important state. It reduces both the effort of circuit building and reducing simulation complexity.

3. Which one of the following is contained in an implication table?
a) Squares
b) Triangles
c) Cubes
d) Circles

Explanation: Implication tables (sometimes referred to as a pair chart) are used to check each pair of states for possible equivalence. The concept is to start assuming every state may be able to combine with every other state. Squares are used to represent states in this method.

4. What is the importance of equivalent states?
a) To simplify the circuitry
b) To change the flow of operation
c) To change the result of the operation
d) To reduce propagation delay

Explanation: State tables are used to describe different states of any finite state machine. If the present state, next state and output of any two states are same then they are called as equivalent states. Any number of equivalent states are simplified to one state to simplify the circuitry.

5. Suppose two equivalent states in a state table have present and next states as (a, b) for both. If one of them has an output e, then what will be the output of the other state?
a) b
b) a
c) e
d) c

Explanation: We know that the output of any two equivalent states in a state table are always equal. Here, given that a and b states are equivalent. So, they must have identical outputs. Hence the output of both the states will be same ‘e’.

6. Which one of the following best describes a sequential machine?
a) An electronic circuit
b) A logic circuit
c) A Moore machine
d) A mathematical model

Explanation: A sequential machine is a mathematical model of a certain type sequential circuit, which has inputs and outputs that can each take on any value from a finite set and are at interest only at certain instants of time. Output depends on both the current as well as the previous input.

7. Which of the following is essential for every sequential model but not for logic circuits?
a) Transmission lines
b) Flip-Flops
c) Memory
d) Switches

Explanation: Sequential machine is a mathematical model of a certain type sequential circuit where output depends on both the current as well as the previous input. So, we need to store the outputs. That’s why a memory circuit is needed.

8. How can we define the behaviour of a synchronous sequential circuit?
a) Discrete instants of time
b) Continuous instants of time
c) Sampling instants of time
d) Any instant

Explanation: Sequential machine is a mathematical model of a certain type sequential circuit where output depends on both the current as well as the previous input. We also need a clock circuit to operate these. Clock inputs are discrete time elements those toggle between on and off. So thus the time instant is discretized and we can only define the states of the circuits at the on states of the clocks.

9. Which one of the following best describes an asynchronous counter model?
a) Common clock is used
b) Every used flip-flop changes state simultaneously
c) Output of the previous flip-flop is set to the clock of the next flip-flop
d) Common clear input is used

Explanation: The word “asynchronous” means that no common clock will be used. Hence no common clock is used in this case. Every output is fed to the clock input of the next flip-flop. Thus, a flip-flop can change it’s state only when its previous flip-flop changes its state.

10. Which of the following is applicable for data flow modelling of VHDL?
a) The flow of data through the entity is expressed using concurrent (parallel) signal
b) The behaviour of an entity as set of statements is executed sequentially in the specified order
c) An entity is described as a set of interconnected components
d) Architecture body is composed of two parts − the declarative part (before the keyword begin) and the statement part (after the keyword begin)

Explanation: VHDL stands for very high-speed integrated circuit hardware description language. It is a programming language used to model a digital system by dataflow, behavioural and structural style of modelling. In dataflow modelling the flow of data through the entity is expressed using concurrent (parallel) signal.

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