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VHDL Multiple Choice Questions | MCQs | Quiz

VHDL Interview Questions and Answers
Practice VHDL questions and answers for interviews, campus placements, online tests, aptitude tests, quizzes and competitive exams.

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•   EDA Tools
•   HDLs Needs
•   VHDL Common Terms
•   Entity & Its Declaration
•   Architecture
•   Data Objects & Types
•   User defined Data Types
•   Data Conversion
•   Operators - 1
•   Operators - 2
•   Behavioural Modelling
•   Behavioural Modelling Types
•   Generics
•   Block Statement
•   Structural Modelling - 1
•   Structural Modelling - 2
•   Structural Modelling - 3
•   VHDL Modelling Types
•   Signal Assignment - 1
•   Signal Assignment - 2
•   Process Statement - 1
•   Process Statement - 2
•   IF Statement
•   Case Statement - 1
•   Case Statement - 2
•   LOOP Statement - 1
•   LOOP Statement - 2
•   Assert Statement
•   WAIT Statements - 1
•   WAIT Statements - 2
•   WAIT Statements - 3
•   Signal vs Variables - 1
•   Signal vs Variables - 2
•   Package
•   Some Predefined Packages
•   Functions & Subprograms-1
•   Functions & Subprograms-2
•   Functions & Subprograms-3
•   Procedures - 1
•   Procedures - 2
•   Attributes
•   Value Kind Attributes
•   Function Kind Attributes
•   Signal Kind Attributes
•   Range Kind Attributes
•   Configurations
•   Overloading
•   Aliases Expressions
•   Generate Statement
•   VHDL Keywords - 1
•   VHDL Keywords - 2
•   VHDL Keywords - 3
•   Functions Flattening
•   ↓ Implementing Gates ↓
•   Different Modelling - 1
•   Different Modelling - 2
•   ↓ VHDL Implementation ↓
•   Sequential Circuits
•   Synchronous Reset
•   Asynchronous Preset
•   Logic Functions - 1
•   Logic Functions - 2
•   Combinational Circuits - 1
•   Combinational Circuits - 2
•   ↓ VHDL Designing ↓
•   Shift Registers
•   Designing Counters
•   Moore Type FSM
•   Mealy Type FSM
•   Top Level System Design
•   RTL Simulation

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VHDL Questions and Answers – Implementing Sequential Circuits with VHDL

Posted on December 5, 2018 by Manish

This set of VHDL written test Questions & Answers focuses on “Implementing Sequential Circuits with VHDL”.

1. A sequential logic can’t be executed by concurrent statements only.
a) True
b) False
View Answer

Answer: a
Explanation: It is true that a sequential logic can’t be executed by concurrent statements only. It requires the sequential statements because they make use of a clock signal.
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2. Which of the following sequential circuit doesn’t need a clock signal?
a) Flip flop
b) Asynchronous counter
c) Shift register
d) Latch
View Answer

Answer: d
Explanation: Latch has an enable input, but no clock signal. All other circuits including asynchronous counter needs a clock signal. It is called asynchronous because every flip flop doesn’t have same clock signal.

3. The following timing diagram shows ______ flip flop.
vhdl-written-test-questions-answers-q3
a) T flip-flop
b) D flip-flop
c) SR flip-flop
d) JK flip-flop
View Answer

Answer: b
Explanation: Since there is only one input to the flip flop, therefore, it can be either D or T flip flop. But, the output becomes equal to input signal as soon as there is a positive edge of the clock therefore, it is a delay flip flop.

4. The process used for implementation of sequential logic in VHDL is called ______ process.
a) Sequential process
b) Combinational process
c) Clocked process
d) Unclocked process
View Answer

Answer: c
Explanation: A process with a clock signal in its sensitivity list is called a clocked process. In case of sequential logic circuit, one needs a clock signal in the sensitivity list.

5. Why do we need to define clock signal in the sensitivity list of the process?
a) To trigger the statement as soon as there is some event on clock
b) To trigger the clock signal as soon as there is some event on input
c) To trigger the clock signal as soon as there is some event on output
d) To trigger the statement as soon as there is some event on input
View Answer

Answer: a
Explanation: To monitor the events on clock signal, whether it is positive triggered circuit or negative triggered circuit, we need to define the clock as a signal in the sensitivity list. When it is in the sensitivity list, then every single positive or negative edge of the signal will trigger the statements inside the process.
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6. A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as_______
a) Switching condition
b) Master slave condition
c) Race around condition
d) Edge triggered condition
View Answer

Answer: c
Explanation: This continuous switching of output between 0 and 1 may be the result of toggle state of the flip flop. This occurs when both the inputs J and K are high and the output toggles its previous state. This condition is called the race around condition.

7. Which of the following method is not used to remove the race around condition in flip flop?
a) Using level triggered flip flop
b) Using master slave flip flop
c) Using edge triggered flip flop
d) All of the above are used to remove the race around
View Answer

Answer: a
Explanation: The race around condition in JK flip flop can be removed by two methods which are using edge triggered flip flop and by using master slave flip flop. However, using level triggered flip flop cause the race around condition.

8. Which of the following attribute is generally used in implementation of sequential circuits?
a) ‘STABLE
b) ‘LENGTH
c) ‘LAST_EVENT
d) ‘EVENT
View Answer

Answer: d
Explanation: Generally ‘EVENT attribute is used in implementation of sequential circuits, because sequential circuit makes use of clock signal which needs to be detected at every positive or negative edge.

9. Which of the following line is correct for detecting positive edge of a clock?
a) IF (clk’EVENT AND clk = ‘0’)
b) IF (clk’EVENT AND clk = ‘1’)
c) IF (clk’EVENT OR clk = ‘0’)
d) IF (clk’EVENT OR clk = ‘1’)
View Answer

Answer: b
Explanation: The correct way to identify the positive edge of the clock signal is shown in option b. The ‘EVENT attribute will detect the event and clk = ‘1’ will check whether its high on clock or not. In this way the positive edge is monitored. We need to use AND operator because both of the conditions should be true.

10. A user doesn’t want to use the IF statement for detecting clock edge. It is possible to do the same by using any other keyword in VHDL.
a) True
b) False
View Answer

Answer: a
Explanation: It is completely possible to detect the clock edge (positive or negative) by any other method than IF statement. One can use the WAIT statement to detect either of the edge of the clock pulse.
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Sanfoundry Global Education & Learning Series – VHDL.

To practice all written questions on VHDL, here is complete set of 1000+ Multiple Choice Questions and Answers.

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VHDL Questions and Answers – Synchronous and Asynchronous Reset »
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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn | Facebook | Twitter

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