This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Designing Shift Registers with VHDL”.
1. Shift registers comprise of which flip-flops?
a) D flip-flops
b) SR flip-flops
c) JK flip-flops
d) T flip-flops
View Answer
Explanation: Shift registers comprise of a few single bit D flip-flops, one flip-flop for one data bit, either logic “1” or a “0”. They are connected together to form a sequence so that the output from the first flip-flop becomes the input of the second flip-flop and so on.
2. In serial input serial output register, the data of ______ is accessed by the circuit.
a) Last flip-flop
b) First flip-flop
c) All flip-flops
d) No flip-flop
View Answer
Explanation: In serial input serial output register, the data of first flip-flop is accessed by the rest of the circuit and in serial input parallel output register, the data of the last flip-flop is accessed by the circuit.
3. In PIPO shift register, parallel data can be taken out by ______
a) Using the Q output of the first flip-flop
b) Using the Q output of the last flip-flop
c) Using the Q output of the second flip-flop
d) Using the Q output of each flip-flop
View Answer
Explanation: In PIPO shift register there are parallel input pins to which data is presented in a parallel format and then the data is transferred to their respective output pins altogether by the same clock pulse. One clock pulse unloads and loads the data of one register, which requires it to use all the output pins of each and every flip-flop.
4. Four bits shift register enables shift control signal in how many clock pulses?
a) Two clock pulses
b) Three clock pulses
c) Four clock pulses
d) Five clock pulses
View Answer
Explanation: One bit is shifted into the register in one clock cycle for data conversion so four bits will be shifted into the register in four clock pulses.
5. Time taken by the shift register to transfer the content is called _______
a) Clock duration
b) Bit duration
c) Word duration
d) Duration
View Answer
Explanation: Serial computer needs less hardware because one circuit can be used over and over again to manipulate the bits that come out of the shift register. The time required by the shift register to shift the entire content is called word duration.
6. Transfer of one bit of information at a time is called _______
a) Rotating
b) Serial transfer
c) Parallel transfer
d) Shifting
View Answer
Explanation: Movement of data at a rate of one bit per clock pulse from one end of the shift register to the other end is called serial transfer. Movement of data into all flip-flops at the same time is called parallel transfer.
7. Clock divider slow down the input clock of the shift register.
a) True
b) False
View Answer
Explanation: Clock divider is also called frequency divider as it divides the input clock frequency and generates the output clock. VHDL code has a clock and resets as input and output as a divided clock.
8. Shift registers are used to delay the data signal.
a) True
b) False
View Answer
Explanation: Shift registers are used to delay the data signal so that it can be used later for a data operation or output. One example could be, equalization of two parallel signals: a data and a data valid indicator. Data valid indicator is commonly used for the delay.
9. In gated D latch, which of the following is the input symbol?
a) D
b) Q
c) EN
d) CLK
View Answer
Explanation: In the gated D latch, D is the data input, EN is active high enable, Q is the data output, CLK is the clock pulse.
10. Which register is used in the following code?
library ieee; use ieee.std_logic_1164.all; entity shift_siso is port (Clock, Sin : in std_logic; Sout : out std_logic); end shift_siso; architecture behav of shift_siso is signal temp: std_logic_vector(7 downto 0); begin process (Clock) begin if (Clock'event and Clock='1') then for i in 0 to 6 loop temp(i+1) <= temp(i); end loop; temp(0) <= Sin; end if ; end process; Sout <= temp(7); end behav;
a) Serial in serial out
b) Serial in parallel out
c) Parallel in parallel out
d) Parallel in serial out
View Answer
Explanation: In the above code, serial in serial out 8-bit register is used. It delays the data and stores it for each register. It may be 64 bits in length, longer if registers and packages are cascaded.
Sanfoundry Global Education & Learning Series – VHDL.
To practice all areas of VHDL, here is complete set of 1000+ Multiple Choice Questions and Answers.
If you find a mistake in question / option / answer, kindly take a screenshot and email to [email protected]
