This set of Computer Fundamentals Multiple Choice Questions & Answers (MCQs) focuses on “Cache Memory”.
1. What is the high speed memory between the main memory and the CPU called?
a) Register Memory
b) Cache Memory
c) Storage Memory
d) Virtual Memory
View Answer
Explanation: It is called the Cache Memory. The cache memory is the high speed memory between the main memory and the CPU.
2. Cache Memory is implemented using the DRAM chips.
a) True
b) False
View Answer
Explanation: The Cache memory is implemented using the SRAM chips and not the DRAM chips. SRAM stands for Static RAM. It is faster and is expensive.
3. Whenever the data is found in the cache memory it is called as _________
a) HIT
b) MISS
c) FOUND
d) ERROR
View Answer
Explanation: Whenever the data is found in the cache memory, it is called as Cache HIT. CPU first checks in the cache memory since it is closest to the CPU.
4. LRU stands for ___________
a) Low Rate Usage
b) Least Rate Usage
c) Least Recently Used
d) Low Required Usage
View Answer
Explanation: LRU stands for Least Recently Used. LRU is a type of replacement policy used by the cache memory.
5. When the data at a location in cache is different from the data located in the main memory, the cache is called _____________
a) Unique
b) Inconsistent
c) Variable
d) Fault
View Answer
Explanation: The cache is said to be inconsistent. Inconsistency must be avoided as it leads to serious data bugs.
6. Which of the following is not a write policy to avoid Cache Coherence?
a) Write through
b) Write within
c) Write back
d) Buffered write
View Answer
Explanation: There is no policy which is called as the write within policy. The other three options are the write policies which are used to avoid cache coherence.
7. Which of the following is an efficient method of cache updating?
a) Snoopy writes
b) Write through
c) Write within
d) Buffered write
View Answer
Explanation: Snoopy writes is the efficient method for updating the cache. In this case, the cache controller snoops or monitors the operations of other bus masters.
8. In ____________ mapping, the data can be mapped anywhere in the Cache Memory.
a) Associative
b) Direct
c) Set Associative
d) Indirect
View Answer
Explanation: This happens in the associative mapping. In this case, a block of data from the main memory can be mapped anywhere in the cache memory.
9. The number of sign bits in a 32-bit IEEE format is ____
a) 1
b) 11
c) 9
d) 23
View Answer
Explanation: There is only 1 sign bit in all the standards. In a 32-bit format, there is 1 sign bit, 8 bits for the exponent and 23 bits for the mantissa.
10. The transfer between CPU and Cache is ______________
a) Block transfer
b) Word transfer
c) Set transfer
d) Associative transfer
View Answer
Explanation: The transfer is a word transfer. In the memory subsystem, word is transferred over the memory data bus and it typically has a width of a word or half-word.
Sanfoundry Global Education & Learning Series – Computer Fundamentals.
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