Embedded Systems Questions and Answers – Cache Memory

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This set of Embedded Systems Multiple Choice Questions & Answers (MCQs) focuses on “Cache Memory”.

1. Which of the following is more quickly accessed?
a) RAM
b) Cache memory
c) DRAM
d) SRAM
View Answer

Answer: b
Explanation: The cache memory is a small random access memory which is faster than a normal RAM. It has a direct connection with the CPU otherwise, there will be a separate bus for accessing data. The processor will check whether the copy of the required data is present in the cache memory if so it will access the data from the cache memory.
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2. Which factor determines the effectiveness of the cache?
a) hit rate
b) refresh cycle
c) refresh rate
d) refresh time
View Answer

Answer: a
Explanation: The proportion of accesses of data that forms the cache hit, which measures the effectiveness of the cache memory.

3. Which of the following determines a high hit rate of the cache memory?
a) size of the cache
b) number of caches
c) size of the RAM
d) cache access
View Answer

Answer: a
Explanation: The size of the cache increases, a large amount of data can be stored, which can access more data which in turn increases the hit rate of the cache memory.

4. Which of the following is a common cache?
a) DIMM
b) SIMM
c) TLB
d) Cache
View Answer

Answer: c
Explanation: The translation lookaside buffer is common cache memory seen in almost all CPUs and desktops which are a part of the memory management unit. It can improve the virtual address translation speed.

5. Which factor determines the number of cache entries?
a) set commutativity
b) set associativity
c) size of the cache
d) number of caches
View Answer

Answer: b
Explanation: The set associativity is a criterion which describes the number of cache entries which could possibly contain the required data.
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6. What is the size of the cache for an 8086 processor?
a) 64 Kb
b) 128 Kb
c) 32 Kb
d) 16 Kb
View Answer

Answer: a
Explanation: The 8086 processor have a 64 Kbytes cache, beyond this size, the cost will be extremely high.

7. How many possibilities of mapping does a direct mapped cache have?
a) 1
b) 2
c) 3
d) 4
View Answer

Answer: a
Explanation: The direct mapped cache only have one possibility to fetch data whereas a two-way system, there are two possibilities, for a three-way system, there are three possibilities and so on. It is also known as the one-way set associative cache.

8. Which of the following allows speculative execution?
a) 12-way set associative cache
b) 8-way set associative cache
c) direct mapped cache
d) 4-way set associative cache
View Answer

Answer: c
Explanation: The direct mapped cache has the advantage of allowing a simple and fast speculative execution.

9. Which of the following refers to the number of consecutive bytes which are associated with each cache entry?
a) cache size
b) associative set
c) cache line
d) cache word
View Answer

Answer: c
Explanation: The cache line refers to the number of consecutive bytes which are associated with each cache entry. The data is transferred between the memory and the cache in a particular size which is called a cache line.
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10. Which factor determines the cache performance?
a) software
b) peripheral
c) input
d) output
View Answer

Answer: a
Explanation: The cache performance is completely dependent on the system and software. In software, the processor checks out each loop and if a duplicate is found in the cache memory, immediately it is accessed.

11. What are the basic elements required for cache operation?
a) memory array, multivibrator, counter
b) memory array, comparator, counter
c) memory array, trigger circuit, a comparator
d) memory array, comparator, CPU
View Answer

Answer: b
Explanation: The cache memory operation is based on the address tag, that is, the processor generates the address which is provided to the cache and this cache stores its data with an address tag. The tag is compared with the address, if they did not match, the next tag is checked. If they match, a cache hit occurs, the data is passed to the processor. So the basic elements required is a memory array, comparator, and a counter.

12. How many divisions are possible in the cache memory based on the tag or index address?
a) 3
b) 2
c) 4
d) 5
View Answer

Answer: c
Explanation: There is four classification based on the tag or index address corresponds to a virtual or physical address. They are PIPT, VIVT, PIVT, VIPT that is, physically indexed physically tagged, virtually indexed virtually tagged, physically indexed virtually tagged, virtually indexed physically tagged respectively.

13. What does DMA stand for?
a) direct memory access
b) direct main access
c) data main access
d) data memory address
View Answer

Answer: a
Explanation: The DMA is direct memory access which can modify the memory without the help of the processor. If any kind of memory access by DMA to be done, it will passes a request to the processor bus and the processor provides an acknowledgment and gives the control of the bus to the DMA.
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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn