This set of VLSI Quiz focuses on “Guidelines for Testability -2”.
1. _______ is used to start the initial sequence correctly.
a) preset
b) clear
c) preset and clear
d) clock
View Answer
Explanation: The sequential logic testing arises at power-up time. To solve this problem and to start the initial sequence correctly, preset and clear are used.
2. Preset and clear is used to
a) initialize only first sequence
b) correct first two sequences
c) correct first and last sequence
d) correct alternative sequences
View Answer
Explanation: Preset and clear is used to initialize only the first sequence as these are very space consuming.
3. How can over-riding the normal initialization state be achieved?
a) by adding preset
b) by adding reset
c) by adding gating in initialize control line
d) by adding sourcing in initialize control line
View Answer
Explanation: The tester should be able to over-ride the normal initialization state of the logic and this can be achieved by the addition of gating in initialize control line.
4. Asynchronous logic is driven by
a) clock
b) gating circuit
c) self-clock
d) self timing
View Answer
Explanation: Asynchronous logic is driven by self-timing state transition in response to changes of the primary input.
5. Which is better in terms of memory storage?
a) synchronous circuits
b) asynchronous circuits
c) sequential circuits
d) clocked circuits
View Answer
Explanation: Synchronous circuits are better when compared to memory storage. Asynchronous circuits have a timing problems and also memory effects and problems.
6. Which circuits are faster?
a) synchronous circuits
b) asynchronous circuits
c) sequential circuits
d) clocked circuits
View Answer
Explanation: Asynchronous circuits are inherently faster than clocked logic but it has other disadvantages like difficult testing, non deterministic behaviour, prones to races, etc.
7. Which is more sensitive logic?
a) synchronous circuits
b) asynchronous circuits
c) sequential circuits
d) clocked circuits
View Answer
Explanation: Asynchronous circuits are more sensitive to tester skews and it is also prone to races and other hazards.
8. Which logic are difficult to design?
a) synchronous circuits
b) asynchronous circuits
c) sequential circuits
d) clocked circuits
View Answer
Explanation: Asynchronous circuit designs are difficult than synchronous logic and must be approached with care, taking the account of critical race and other hazard-generating conditions.
9. Automatic test pattern generators depend on
a) map design
b) layout design
c) logic domain
d) testing domain
View Answer
Explanation: Automatic test pattern generators work in logic domain and view delay-dependent logic as redundant combinational logic.
10. When a clock signal is gated with another signal like load signal, output is not affected.
a) true
b) false
View Answer
Explanation: When a clock signal is gated with another signal such as load signal, then any skew on that signal can cause the erroneous output from associated logic.
Sanfoundry Global Education & Learning Series – VLSI.
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