This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Asynchronous Preset and Clear”.
1. What type of inputs is preset and clear?
a) Data input
c) Clock input
d) Control input
Explanation: Preset (PRE) and clear (CLR) are asynchronous control inputs, which means output responds to these inputs immediately because they have control over the output that is because they are not synchronized by an external clock.
2. Clear (CLR) or preset (PRE) with a bar above them shows that they have ________
a) Active high input
b) Active low input
c) Clocked input
d) No input
Explanation: The inversion bar over the designations of preset and clear shows that they have active LOW asynchronous inputs. If the preset input is active low, then the output of the flip-flop is set to one. If the clear input is active low, then the output of the flip-flop is reset to 0.
3. Asynchronous inputs are also called override inputs.
Explanation: Asynchronous inputs change the state of the flip-flop regardless of the clock input, they override inputs which can force a particular state onto the flip-flop that’s why they are also called override inputs.
4. The output of the flip-flop _______ when both the input, preset and clear are active low at the same time.
a) Is set to 1
b) Is set to 0
c) Becomes X (Don’t care)
d) Is controlled by clock
Explanation: If preset is active low then Q=1, Q’=0. If clear is active low Q=0, Q’=1. It is not possible to preset and clear a flip-flop at the same time because Q can’t be 0 and 1 at the same instant of time, hence the output of the flip-flop will become X, which is don’t care.
5. What is the state of PRESET input?
d) Don’t care
Explanation: After the preset input is activated, the flip-flop will be SET i.e. Q=1 and Q’=0 without considering any synchronous input or clock input. So the state of the preset input is set.
6. What is the state of CLEAR input?
d) Don’t care
Explanation: After the clear input is activated, the flip-flop will be RESET i.e. Q=0 and Q’=1 without considering any synchronous input or clock input. The flip-flop will go back to its initial state.
7. What happens if both the inputs PRE and CLR are activated?
a) Flip-flop is reset
b) Flip-flop is set
c) Invalid State
d) No output
Explanation: If preset input and clear input both are activated in the flip-flop then, Q and Q’ go to the same state simultaneously which is not possible. Hence, then flip-flop gives an invalid state as the output.
8. Which of the following input on a flip-flop has control over the outputs?
a) Data input
Explanation: Preset is an asynchronous input, it has the control over the output while synchronous inputs have control over the output ONLY in step, or in sync with the clock signal transitions.
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