This set of VHDL Questions and Answers for Campus interviews focuses on “Functions and Subprograms – 3”. 1. In VHDL it is not possible to use recursive functions. a) True b) False 2. Apart from using WAIT statements, which of the following is not possible in functions? a) Variable assignment b) Return statement c) Variable … Read more
This set of VHDL Questions and Answers for Entrance exams focuses on “Functions and Subprograms – 2”. 1. Refer to the function defined below, a and b have respectively following data objects. FUNCTION my_func (SIGNAL a : STD_LOGIC_VECTOR; b : STD_LOGIC) RETURN BOOLEAN IS …..; a) Constant, Constant b) Constant, Signal c) Signal, Constant d) … Read more
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Functions and Subprograms – 1”. 1. Functions and subprograms are both same. a) True b) False 2. A function is a ________ code. a) Concurrent b) Sequential c) Concurrent as well as sequential d) Process oriented 3. Which of the following sequential statement … Read more
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Some Predefined Packages”. 1. Which of the following package need not to be a part of the VHDL code? a) STANDARD b) STD_LOGIC_1164 c) TEXTIO d) STD_LOGIC_ARITH 2. In which of the following library, the package STANDARD defined? a) IEEE b) STD c) … Read more
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Package”. 1. Which of the following is true about packages? a) Package is collection of libraries b) Library is collection of packages c) Package is collection of entities d) Entity is collection of packages 2. A package may consist of _________ design units. … Read more
This set of VHDL online quiz focuses on “Signal vs Variables – 2”. 1. Which data object can’t be declared inside a process? a) Signal b) Variable c) Constant d) Integer 2. When a signal is assigned a value inside a process, then the value of a signal is updated _________ a) Immediately b) After … Read more
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Signal vs Variables – 1”. 1. Which of the following is the correct use of the signal? a) To set a default value b) To pass value between circuits c) To declare a variable d) To represent local information 2. What is the … Read more
This set of VHDL Question Bank focuses on “WAIT Statements – 3”. 1. Which of the following is true about WAIT UNTIL statement? a) WAIT UNTIL statement is supported by synthesis tools b) WAIT UNTIL statement is not supported by synthesis tools c) WAIT UNTIL statement is supported in a clocked process only d) WAIT … Read more
This set of VHDL online test focuses on “WAIT Statements – 2”. 1. Which of the following statement uses only 1 signal? a) WAIT FOR b) WAIT UNTIL c) WAIT ON d) WAIT UNTIL and WAIT FOR 2. Given that a process has no sensitivity list and has only one WAIT statement which is WAIT … Read more
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “WAIT Statements – 1”. 1. WAIT statement can’t appear under _______ directly. a) Architecture b) Process c) Procedure d) Subprogram 2. Which of the following can’t be used in a process when it has any WAIT statement? a) IF b) CASE c) LOOP … Read more
