This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Common Terms used in VHDL”.
1. Which of the following is the basic building block of a design?
Explanation: Entity is the basic building block; all the information regarding input and output of the circuit to be designed is declared in Entity.
2. A package in VHDL consists of _________
a) Commonly used architectures
b) Commonly used tools
c) Commonly used data types and subroutines
d) Commonly used syntax and variables
Explanation: Package is a collection of all the commonly used data types and subroutines so that programmer can easily use them in their design without defining the same functions again and again.
3. Complete description of the circuit to be designed is given in _________
Explanation: Architecture completely describes the circuit; while entity describes just the input and output of the design. Architecture may describe the behavior of the circuit or its structure.
4. An entity can have more than one architecture.
Explanation: Yes, An entity can have more than one architecture. One may define its behaviour and other may define its structure or dataflow. But, the converse of this statement is not true i.e. One architecture can’t define more than one entities.
5. What is the use of Configuration statement?
a) To configure the components exactly in design
b) To complete the design process by adding libraries
c) To add more than one entities into a single architecture
d) To add some component in any entity architecture pair
Explanation: Configuration statement is used to bind any component instance with entity architecture pair. It is used to describe the behavior, which is used in almost each entity.
6. In VHDL, Bus is a type of ________
Explanation: Bus is a special kind of signal. It may have its drivers turned off.
7. What is the use of Generics in VHDL?
a) To turn on and off the drivers
b) To pass information to the entity
c) To describe architecture
d) To divide code into small processes
Explanation: Generics are used to pass the information to entity through parameters. In short, Generics are parameters which passes information to entity. For example, entity has variables for rise time and fall time delay; then the values for both delays can be passed by using Generics.
8. Driver can be seen as a _______ of the signal.
c) Final value
Explanation: Driver is a source on the signal. All of the signals are driven by their Drivers. Any signal may have more than one driver too.
9. Predefined data for an VHDL object is called ________
Explanation: Attribute is the predefined datatype associated with any VHDL object. For example, operating temperature of any device will be its attribute.
10. A process is the basic unit of execution in VHDL.
Explanation: All the operations in the VHDL description are divided into processes during simulation and therefore, Process is the basic unit of execution.
11. Which of the following describes the structure of VHDL code correctly?
a) Library Declaration; Entity Declaration; Architecture Declaration; Configurations
b) Entity Declaration; Configuration; Library Declaration; Architecture Declaration
c) Configuration; Library Declaration; Entity Declaration; Architecture Declaration
d) Library Declaration; Configuration; Entity Declaration; Architecture Declaration
Explanation: In any VHDL code, first of all, we have to define libraries and packages we want to use. After Library Declaration part, Entities are declared. When Entities are created, then only we can describe its architecture. Last part in any VHDL code is Configuration.
12. Which of the following statement is true?
a) Package is a collection of Libraries
b) Library is a collection of Packages
c) Entity is a collection of Packages
d) Architecture is a collection of Entities
Explanation: A library consists of many packages which in turn is a collection of data types and subroutines. Entity is a collection of signals and variables and architecture describes the behavior or structure of Entity.
13. Which of the following is used at the end of a statement?
a) ; (Semicolon)
b) — ( double hyphen)
c) _ (underscore)
d) No sign is used at the end of statement
Explanation: Semicolon is the sign used at the end of any statement. Double hyphen is used for writing a comment which means wherever we have sign of double hyphen(–), the simulator will skip that line and start compiling from the next line.
14. The correctly declared library for VHDL code is ________
LIBRARY library_name; USE package_name.parts;
LIBRARY package_name.parts; LIBRARY library_name;
USE library_name; LIBRARY library_name.package_name.parts
LIBRARY library_name; USE library_name.package_name.parts
Explanation: Library declaration is completed in two lines. First line declares the library and in second line we use ‘USE’ clause to define the package name we want to use from the respective library and the parts we want to use. For example, LIBRARY ieee; USE ieee.std_logic_1164.all; In this declaration, ieee is library and std_logic_1164 package is used; all in package part section specifies that all parts of package are used.
15. One can’t use more than one library in the VHDL code.
Explanation: There is no restriction on the number of libraries we want to use. One can define more than one library in VHDL code.
Sanfoundry Global Education & Learning Series – VHDL.
To practice all areas of VHDL, here is complete set of 1000+ Multiple Choice Questions and Answers.