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VHDL Multiple Choice Questions | MCQs | Quiz

VHDL Interview Questions and Answers
Practice VHDL questions and answers for interviews, campus placements, online tests, aptitude tests, quizzes and competitive exams.

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•   EDA Tools
•   HDLs Needs
•   VHDL Common Terms
•   Entity & Its Declaration
•   Architecture
•   Data Objects & Types
•   User defined Data Types
•   Data Conversion
•   Operators - 1
•   Operators - 2
•   Behavioural Modelling
•   Behavioural Modelling Types
•   Generics
•   Block Statement
•   Structural Modelling - 1
•   Structural Modelling - 2
•   Structural Modelling - 3
•   VHDL Modelling Types
•   Signal Assignment - 1
•   Signal Assignment - 2
•   Process Statement - 1
•   Process Statement - 2
•   IF Statement
•   Case Statement - 1
•   Case Statement - 2
•   LOOP Statement - 1
•   LOOP Statement - 2
•   Assert Statement
•   WAIT Statements - 1
•   WAIT Statements - 2
•   WAIT Statements - 3
•   Signal vs Variables - 1
•   Signal vs Variables - 2
•   Package
•   Some Predefined Packages
•   Functions & Subprograms-1
•   Functions & Subprograms-2
•   Functions & Subprograms-3
•   Procedures - 1
•   Procedures - 2
•   Attributes
•   Value Kind Attributes
•   Function Kind Attributes
•   Signal Kind Attributes
•   Range Kind Attributes
•   Configurations
•   Overloading
•   Aliases Expressions
•   Generate Statement
•   VHDL Keywords - 1
•   VHDL Keywords - 2
•   VHDL Keywords - 3
•   Functions Flattening
•   ↓ Implementing Gates ↓
•   Different Modelling - 1
•   Different Modelling - 2
•   ↓ VHDL Implementation ↓
•   Sequential Circuits
•   Synchronous Reset
•   Asynchronous Preset
•   Logic Functions - 1
•   Logic Functions - 2
•   Combinational Circuits - 1
•   Combinational Circuits - 2
•   ↓ VHDL Designing ↓
•   Shift Registers
•   Designing Counters
•   Moore Type FSM
•   Mealy Type FSM
•   Top Level System Design
•   RTL Simulation

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VHDL Questions and Answers – Common Terms used in VHDL

Posted on December 5, 2018 by Manish

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Common Terms used in VHDL”.

1. Which of the following is the basic building block of a design?
a) Architecture
b) Entity
c) Process
d) Package
View Answer

Answer: b
Explanation: Entity is the basic building block; all the information regarding input and output of the circuit to be designed is declared in Entity.
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2. A package in VHDL consists of _________
a) Commonly used architectures
b) Commonly used tools
c) Commonly used data types and subroutines
d) Commonly used syntax and variables
View Answer

Answer: c
Explanation: Package is a collection of all the commonly used data types and subroutines so that programmer can easily use them in their design without defining the same functions again and again.

3. Complete description of the circuit to be designed is given in _________
a) Architecture
b) Entity
c) Library
d) Configurations
View Answer

Answer: a
Explanation: Architecture completely describes the circuit; while entity describes just the input and output of the design. Architecture may describe the behavior of the circuit or its structure.

4. An entity can have more than one architecture.
a) True
b) False
View Answer

Answer: a
Explanation: Yes, An entity can have more than one architecture. One may define its behaviour and other may define its structure or dataflow. But, the converse of this statement is not true i.e. One architecture can’t define more than one entities.

5. What is the use of Configuration statement?
a) To configure the components exactly in design
b) To complete the design process by adding libraries
c) To add more than one entities into a single architecture
d) To add some component in any entity architecture pair
View Answer

Answer: d
Explanation: Configuration statement is used to bind any component instance with entity architecture pair. It is used to describe the behavior, which is used in almost each entity.

6. In VHDL, Bus is a type of ________
a) Signal
b) Constant
c) Variable
d) Driver
View Answer

Answer: a
Explanation: Bus is a special kind of signal. It may have its drivers turned off.
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7. What is the use of Generics in VHDL?
a) To turn on and off the drivers
b) To pass information to the entity
c) To describe architecture
d) To divide code into small processes
View Answer

Answer: b
Explanation: Generics are used to pass the information to entity through parameters. In short, Generics are parameters which passes information to entity. For example, entity has variables for rise time and fall time delay; then the values for both delays can be passed by using Generics.

8. Driver can be seen as a _______ of the signal.
a) Part
b) Type
c) Final value
d) Source
View Answer

Answer: d
Explanation: Driver is a source on the signal. All of the signals are driven by their Drivers. Any signal may have more than one driver too.

9. Predefined data for an VHDL object is called ________
a) Generic
b) Constant
c) Attribute
d) Library
View Answer

Answer: c
Explanation: Attribute is the predefined datatype associated with any VHDL object. For example, operating temperature of any device will be its attribute.

10. A process is the basic unit of execution in VHDL.
a) True
b) False
View Answer

Answer: a
Explanation: All the operations in the VHDL description are divided into processes during simulation and therefore, Process is the basic unit of execution.

11. Which of the following describes the structure of VHDL code correctly?
a) Library Declaration; Entity Declaration; Architecture Declaration; Configurations
b) Entity Declaration; Configuration; Library Declaration; Architecture Declaration
c) Configuration; Library Declaration; Entity Declaration; Architecture Declaration
d) Library Declaration; Configuration; Entity Declaration; Architecture Declaration
View Answer

Answer: a
Explanation: In any VHDL code, first of all, we have to define libraries and packages we want to use. After Library Declaration part, Entities are declared. When Entities are created, then only we can describe its architecture. Last part in any VHDL code is Configuration.

12. Which of the following statement is true?
a) Package is a collection of Libraries
b) Library is a collection of Packages
c) Entity is a collection of Packages
d) Architecture is a collection of Entities
View Answer

Answer: b
Explanation: A library consists of many packages which in turn is a collection of data types and subroutines. Entity is a collection of signals and variables and architecture describes the behavior or structure of Entity.
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13. Which of the following is used at the end of a statement?
a) ; (Semicolon)
b) — ( double hyphen)
c) _ (underscore)
d) No sign is used at the end of statement
View Answer

Answer: a
Explanation: Semicolon is the sign used at the end of any statement. Double hyphen is used for writing a comment which means wherever we have sign of double hyphen(–), the simulator will skip that line and start compiling from the next line.

14. The correctly declared library for VHDL code is ________
a)

LIBRARY library_name;
USE package_name.parts;

b)

LIBRARY package_name.parts;
LIBRARY library_name;

c)

USE library_name;
LIBRARY library_name.package_name.parts

d)

LIBRARY library_name;
USE library_name.package_name.parts
View Answer
Answer: d
Explanation: Library declaration is completed in two lines. First line declares the library and in second line we use ‘USE’ clause to define the package name we want to use from the respective library and the parts we want to use. For example, LIBRARY ieee; USE ieee.std_logic_1164.all; In this declaration, ieee is library and std_logic_1164 package is used; all in package part section specifies that all parts of package are used.
 
 

15. One can’t use more than one library in the VHDL code.
a) True
b) False
View Answer

Answer: b
Explanation: There is no restriction on the number of libraries we want to use. One can define more than one library in VHDL code.

Sanfoundry Global Education & Learning Series – VHDL.

To practice all areas of VHDL, here is complete set of 1000+ Multiple Choice Questions and Answers.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn | Facebook | Twitter

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