This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Synchronous and Asynchronous Reset”.
1. Reset is a signal that is used for the initialization of the hardware.
a) True
b) False
View Answer
Explanation: Hardware is not capable of doing the initialization on its own, so reset is used to initialize the hardware in the beginning. Reset clears any pending event or errors in the system and brings it back to its initial state.
2. How many types of resets are there in hardware design?
a) One
b) Two
c) Three
d) Four
View Answer
Explanation: There are two types of resets in hardware designs: Asynchronous reset and synchronous reset. Asynchronous reset works independently of the clock while synchronous reset works with respect to the clock.
3. In synchronous reset, reset is sampled with respect to _______
a) Enable signal
b) Data input signal
c) Clock signal
d) Output signal
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Explanation: In synchronous reset, the reset signal is sampled with respect to the clock signal. After the reset signal is enabled, it won’t change until the next active clock edge. The output will change only with the positive edge of the clock.
4. Which of the following is an advantage of a synchronous reset?
a) It is slow
b) It requires a clock signal to reset the circuit
c) It filters the reset signal
d) It needs a stretched reset
View Answer
Explanation: Synchronous reset filters the reset signal. It prevents the circuit from glitches and results in smooth functioning. Glitches don’t happen in synchronous reset because it is in synchronization with the clock signal.
5. In asynchronous reset, reset is sampled independently of the _______
a) Enable signal
b) Data input signal
c) Clock signal
d) Output signal
View Answer
Explanation: In asynchronous reset, reset is sampled independently of the clock signal. It means, after the reset signal is enabled, it will start effective immediately and it will not wait or check for the clock edges.
6. Synchronous reset is a fast reset.
a) True
b) False
View Answer
Explanation: Synchronous reset is slow as it requires clock signal due to which it experience clock cycle related latency. Asynchronous rest is a fast reset since it can be reset without a clock signal and hence high speeds can be achieved.
7. Which of the following is NOT an advantage of asynchronous reset?
a) It is fast
b) It doesn’t require a clock signal to reset the circuit
c) Reset gets the highest priority
d) It may cause metastability
View Answer
Explanation: Asynchronous reset doesn’t require an active clock signal to get flip-flops to a known state, it also has a lower latency as compared to synchronous reset due to which flip-flops behave in a non-predictive manner. The reset signal must be synchronized with the clock, when it is not, it causes metastability issues.
8. Asynchronous circuit is also called ________ circuit.
a) Combinational
b) Self-timed
c) Clock circuit
d) Delayed
View Answer
Explanation: Asynchronous circuit is also called self-timed circuit because it is not governed by a global clock signal, it mostly uses signals which show completion of operations and instructions, defined by simple data transfer protocols.
9. Designation used by a flip-flop for the reset is ________
a) PRE
b) CLR
c) D
d) Q
View Answer
Explanation: The flip-flop is SET when the preset (PRE) input is activated without considering the synchronous inputs or the clock. The flip-flop is RESET when the clear (CLR) input is activated without considering the synchronous inputs or the clock.
10. Preset and clear are asynchronous inputs.
a) True
b) False
View Answer
Explanation: Preset (PRE) and clear (CLR) are asynchronous inputs as they work regardless of the clock input signal. They can set or reset the flip-flop without concerning about the status of the clock.
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