VHDL Questions and Answers – Flattening and Factoring of Functions


This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Flattening and Factoring of Functions”.

1. What is the process of flattening?
a) Converting an optimized function to unoptimized form
b) Converting a Boolean function to PAL format
c) Converting a Boolean function to PLA format
d) Converting a Boolean function to POS form
View Answer

Answer: c
Explanation: Flattening is a process of converting the unoptimized Boolean description into a PLA format. PLA format is a format in which the description is converted into sum of products form i.e. in the form of OR and AND arrays.

2. Flattening creates a flat signal representation of ______ levels.
a) 1
b) 2
c) 3
d) 4
View Answer

Answer: b
Explanation: Flattening is named so because it creates a flat signal representation of only two levels: an AND level and an OR level. Because it converts the function into PLA form in which we can implement only sum of products.

3. How will you flatten the following function?

a = b AND c;
b = x OR (y AND z);
c = q OR w;

a) a = (x AND q) OR (q AND y AND z) OR (w AND x) OR (w AND y AND z);
b) a = (x OR q) AND (q OR y OR z) AND (w OR x) AND (w OR y OR z);
c) a = (x AND b) OR (c AND y AND z) OR (c AND x) OR (b AND y AND z);
d) a = (w AND q) OR (w AND y AND z) OR (q AND x) OR (q AND y AND z);
View Answer

Answer: a
Explanation: Flattening means only two levels which are AND and OR arrays. So, there must be no intermediate levels. For example, in the question given above, b and c are two intermediate signals used. So, first b and c must be solved then only a can be solved. Therefore, flattening will give the resultant shown in option a. It is Boolean equivalent of the first without any intermediate node.

4. What is the result of flattening of functions?
a) Increased readability
b) Increased speed
c) Decreased speed
d) Decreased readability
View Answer

Answer: b
Explanation: Flattening of functions increase the speed of functions. Since there are no intermediate nodes, there are few logic levels from the input to the output. It is only good for smaller functions in which numbers of terms are not more.

5. In which of the following functions, the flattening is difficult?
a) Functions containing many XOR
b) Functions which are already minimal
c) Functions which are slow due to intermediate nodes
d) Functions which is always false
View Answer

Answer: a
Explanation: In case, when a function has many numbers of terms, especially with XOR functions. Because a n- input EXOR gate needs 2^(n-1) terms. Due to which it becomes much complicated to convert that particular function into flattened PLA form. Due to this reason the speed decreases.

6. Which of the following is the opposite of flattening of functions?
a) Structure
b) Adding intermediate nodes
c) Un-flattening
d) Factoring
View Answer

Answer: d
Explanation: Factoring is the process of adding intermediate terms or nodes to add structure to a description. So, factoring is exactly opposite of flattening in which the intermediate nodes are removed and made a single PLA function.

7. The main advantage of using factoring is ________
a) Reducing the speed
b) Reducing the number of terms
c) Adding intermediate nodes
d) Reducing flattening
View Answer

Answer: b
Explanation: The main disadvantage of flattening is that it confuses the whole function by adding more number of terms in one expression which decreases the speed. To overcome this disadvantage, factoring is used to reduce the number of terms in the expression.

8. What is another name for the factoring of functions?
a) De-flattening
b) Intermediation
c) Structuring
d) De-structuring
View Answer

Answer: c
Explanation: Factoring is also known as structuring. This is the name given to factoring because it structures the expressions and increases their readability. It basically uses the concept of factoring used in mathematics to do so.

9. Which factor can be there in the following two functions?

x = a AND b OR a AND c;
y = b OR c OR d

a) a AND b
b) b OR a
c) b AND c
d) b OR c
View Answer

Answer: d
Explanation: After factoring, using various Boolean properties, the term b or c can be factored out to a separate intermediate node. In the first expression, if we see it is equivalent to a AND (b or c). Also, b OR c is a part of second expression as well.

10. What would be the ideal case for a design?
a) Using factoring only
b) Using flattening only
c) Using both flattening and factoring
d) Neither using flattening and nor factoring
View Answer

Answer: c
Explanation: Since factoring will add an intermediate node which can reduce speed. On the other hand, the flattening process will increase the speed. But, at the same time flattening can increase the area and decrease the fan-out. This is completely opposite to factoring which reduces the area and increases the fan-out.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn | Youtube | Instagram | Facebook | Twitter