This set of VHDL Question Bank focuses on “WAIT Statements – 3”.
1. Which of the following is true about WAIT UNTIL statement?
a) WAIT UNTIL statement is supported by synthesis tools
b) WAIT UNTIL statement is not supported by synthesis tools
c) WAIT UNTIL statement is supported in a clocked process only
d) WAIT UNTIL statement is supported in a combinational process
View Answer
Explanation: Most of the synthesis tools support a single WAIT UNTIL statement in a clocked process only. That means WAIT UNTIL statement can be mostly used for implementing the sequential circuit or system.
2. Which of the following is true about WAIT ON statement?
a) WAIT ON statement is supported by synthesis tools
b) WAIT ON statement is not supported by synthesis tools
c) WAIT ON statement is supported in a clocked process only
d) WAIT ON statement is supported in a combinational process
View Answer
Explanation: Some tools support a single WAIT ON statement as an alternative to a sensitive list in a combinational process or the process in which there is no clock signal. Therefore, WAIT ON is useful for combinational circuits.
3. In a procedure, __________ statement is not supported.
a) WAIT UNTIL
b) WAIT ON
c) WAIT FOR
d) WAIT FOR and unconditional WAIT
View Answer
Explanation: In any procedure, the wait statements can be used (given that the procedure is not called from the process with a sensitive list). But, the WAIT FOR and simple WAIT or unconditional WAIT statement is not supported by synthesis tools inside the procedure.
4. What kind of circuit is implemented by the following architecture?
ARCHITECTURE my_arch OF my_design IS BEGIN PROCESS BEGIN WAIT ON clk; IF(clk = ‘1’) THEN y <= x; END IF; END PROCESS; END my_arch;
a) D flip flop
b) Inverter
c) OR gate
d) Shift register
View Answer
Explanation: Since the process is using a clock and a WAIT ON statement, so it is a sequential circuit. Also, the process is sensitive to clock. Whenever, any event on clock occurs, the process is resumed and checked if clock is one or not. If it is one, then the value of input is transferred to the output. So, clearly this is a D flip flop.
5. WAIT FOR statement is useful only for _________
a) Synthesis
b) Simulation
c) Gate level implementation
d) Optimization
View Answer
Explanation: WAIT FOR statement is only good for simulation, you can’t synthesize it. Since, synthesis means to convert the logic into actual hardware circuit. If you are using WAIT FOR 10 ns, certainly, this can’t be used in a synthesis process. So, WAIT FOR can be used for simulation only.
6. A user wants to assign a signal after a wait of 20 ns. The process used has a sensitivity list. What is the possible way to achieve this?
a) By using WAIT FOR statement
b) By using AFTER clause
c) By using a separate process
d) By using WAIT ON statement
View Answer
Explanation: As we know that a process can’t contain both a sensitivity list and a WAIT statement. So, WAIT FOR can’t be used in this case. Also, AFTER clause is ignored by synthesis tool when used inside a process. So, using AFTER is also not possible. The only way to do this is using another process which can communicate with this process.
7. Since WAIT statement can’t be synthesized many times, how a clock event can be detected then?
a) By using IF(clk = ‘1’)
b) By using ‘EVENT keyword
c) By using a CASE statement
d) By using a LOOP
View Answer
Explanation: The clock can be detected by ‘EVENT keyword. One can use IF in conjunction with ‘EVENT to detect the clock event and high and low on the same. For example, IF(clk’EVENT AND clk = ‘1’) will detect the rising edge of the clock.
8. A wait statement can have label preceding it.
a) True
b) False
View Answer
Explanation: In VHDL 93, it is possible to use a label in front of WAIT statement. In that case, the syntax is as follows:
Label : WAIT {UNTIL | ON | FOR} {condition | signal | time_expression};
9. Which of the following can be used to make the process wait indefinitely?
a) WAIT FOR indefinite ns;
b) WAIT UNTIL false;
c) WAIT;
d) WAIT UNTIL true;
View Answer
Explanation: When the WAIT is used without any clause following it then it is used as an infinite WAIT statement. The WAIT statement without any clause makes the process to wait indefinitely as there is no condition or signal or time period specified.
Sanfoundry Global Education & Learning Series – VHDL.
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