This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Behavioural Modelling”.
1. The most basic form of behavioral modeling in VHDL is_______
a) IF statements
b) Assignment statements
c) Loop statements
d) WAIT statements
Explanation: Assignment statements are used basically in the behavioral modeling. In behavioral modeling, one needs to describe the value of outputs for various combinations of inputs, so we need to assign different values to output variables. Therefore, assignment is the most used statement in behavioral modeling.
2. For any concurrent assignment statement, which of the following is true?
a) The statement is executed once
b) The statement is executed twice
c) The value of left operand is assigned to right operand
d) The statement is executed as many times as the value changes
Explanation: A concurrent assignment statement assigns the value of right operand to left operand and this statement is executed many times. Whenever the value of right operand is changed, the assignment statement is executed.
3. a <= b after 10ns; In this statement the keyword ‘after’ is used for introducing delay.
Explanation: The keyword ‘after’ is used for introducing delay in the assignment statement. Whenever the value of b is changed, the value of a is changed after 10ns. This 10ns is helpful while creating square waveform.
4. Which of the circuit is described by following code?
LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY my_func IS PORT(x, a, b : IN std_logic; q : OUT std_logic); END my_func; ARCHITECTURE behavior OF my_func IS SIGNAL s : INTEGER; BEGIN WITH s SELECT q <= a AFTER 10 ns WHEN 0; b AFTER 10 ns WHEN 1; s <= 0 WHEN x = ‘0’ ELSE 1 WHEN x = ‘1’; END behavior;
a) AND gate
b) OR gate
c) MUX 2:1
d) DEMUX 1:2
Explanation: In this code, the behavior of 2:1 MUX is explained. By using WITH statement, the output is selected by the use of select line. Here, s is used as select line and x is considered as the value of select line. Also, a and b are taken as two inputs and q as output.
5. The main problem with behavioral modeling is ________
a) Asynchronous delays
c) No delay
d) Supports single driver only
Explanation: In behavioral modeling, there are different types of delays and this can create problem in functioning of system. Sometimes zero delay events are used to produce consistent results. If these are not properly ordered, results can be disparate between different simulations.
6. What is the use of simulation deltas in VHDL code?
a) To create delays in simulation
b) To assign values to signals
c) To order some events
d) Evaluate assignment statements
Explanation: Simulation deltas are used to order some specific events to avoid complications in simulations. Especially, in zero delay events, they are properly ordered so as to produce consistent results. It is actually a complex delay model used for zero delay events.
7. VHDL can’t handle multiply driven signals.
Explanation: A multiply driven signal is the one which has more than one driver. VHDL can handle these signals easily and in a unique way. These multiply driven signals are useful for modeling various data bus and bidirectional bus etc.
8. Which function is used to create a single value for multiple driver signals?
a) Resolution function
c) Concurrent assignments
d) Sequential assignments
Explanation: The values of all the drivers are resolved together to create a single value for the signal. The method of resolving all the drivers is through a resolution function which is a designer writer function. That function is called whenever any one of the driver changes its value.
9. Refer to the code given below, which of the following signal is driven by multiple drivers?
LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY function IS PORT (b, c : IN BIT; a, d : OUT BIT); END function; ARCHITECTURE behavior OF my_func IS BEGIN a <= b; a <= c; d <= b; END behavior;
Explanation: A signal is called multiply driven signals if it is driven by more than one signals or the value of signal changes with respect to more than one signal. Here, the value of a changes when the value of b or value of c changes. Therefore, a is driven by two drivers named as b and c. Each concurrent statement creates a driver for left operand.
10. A signal is a is driven by two signals b and c. How the value of b and c will be resolved to calculate the value of a?
a) By short circuiting both driver
b) By open circuiting one driver
c) By AND operation between two drivers
d) By NOT operation of both drivers
Explanation: The value of multiple driver signal is found by using resolution function. The default resolution function short circuits all the drivers and performs OR operation which means any change in any driver will cause change in output signal. The value of delays is also taken into consideration.
Sanfoundry Global Education & Learning Series – VHDL.
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