This set of VHDL Questions and Answers for Experienced people focuses on “Structural Modeling – 2”.
1. In which part of VHDL code, components must be declared?
Explanation: The component can be declared only after entity declaration or in the package itself. So, components can be declared either in architecture or in package. If the component is declared in package, then just include the package and don’t declare it again in architecture body.
2. Which of the following function is used to map the component?
a) COMPONENT INSTANTIATE
b) PORT MAP
c) GENERIC MAP
Explanation: To map a component in the circuit, first it needs to be declared. Once it is declared, one can use the PORT MAP function to map the port on the design. This function can have as many arguments as the number of ports in the component.
3. How many ways are there in VHDL to map the components?
Explanation: There are two ways by which one can map the components in VHDL design excluding the mapping of generic units. One method is positional mapping and another mapping is nominal mapping. Positional mapping is generally used mapping.
4. What is the property of Positional mapping?
a) Easier to write
b) Less error prone
c) Ports can be left unconnected
d) Difficult to write
Explanation: Positional mapping is a type of component mapping which is generally used in VHDL and it is easier to write. But, positional mapping has slightly more chances of occurrence of an error.
5. __________ mapping is less error prone
Explanation: Nominal mapping has less chances of error since every port is assigned the specific value which is not the case with positional mapping. So, nominal mapping can take time but it is less prone to errors.
6. A component has 3 ports- two inputs(a and b) and one output(y). Which of the following statement is for the positional mapping of the component?
a) LABEL : my_component PORT MAP (l, m, n);
b) LABEL : my_component PORT MAP (y, a);
c) LABEL : my_component PORT MAP (l => a, m => b, n => y);
d) LABEL : my_component PORT MAP(a, b, y>= a);
Explanation: A component can be instantiated by using positional or nominal mapping. In case of positional mapping, arguments are written, in this case, 3 arguments among which first two must be taken as input and last one is taken as output port. SO, only option a is using the positional mapping in which l and m corresponds to a and b respectively and n corresponds to y.
7. The ports of a component can be left unconnected.
Explanation: In VHDL, It is possible to leave any port unconnected. If our requirement is to leave a port unconnected in the circuit, then it can be done by using a keyword ‘OPEN’. By doing so, the port will not be connected to any input or output.
8. Which of the following is a right way to leave a port unconnected?
a) L1 : my_component PORT MAP(a); a <= OPEN;
b) L1 : my_component PORT MAP(a := OPEN);
c) L1: my_component PORT MAP(a => OPEN);
d) L1 : my_component PORT MAP(a); a := OPEN;
Explanation: To leave any port unconnected the keyword used Is ‘OPEN’. This keyword can be used only in the arguments of the function PORT MAP() by using “=>” operator. Therefore, option c is the right way to use keyword OPEN.
9. It is not necessary that the order of the arguments in PORT MAP is taken as the order in which ports are declared.
Explanation: The order of arguments is taken as the order of ports declared in the component declaration in case of positional mapping. For example, the following statement declares a component-
COMPONENT my_component IS PORT ( a, b, c : IN BIT; x, y : OUT BIT); END COMPONENT; U1: my_component PORT MAP(p, q, r, s, t);
Here, in the component instantiation statement p, q, r, s and t will corresponds to a, b, c, x and y respectively because of the order used at the time of declaration is inherited in the component instantiation statement.
10. How to declare a 2 input OR gate in the structural modeling?
COMPONENT or IS PORT ( a, b : IN BIT; x, y : OUT BIT); END COMPONENT;
COMPONENT or IS PORT ( a, b : IN BIT; y : OUT BIT); END COMPONENT;
COMPONENT or_gate IS PORT ( a, b : IN BIT; x, y : OUT BIT); END COMPONENT;
COMPONENT or_gate IS PORT ( a, b : IN BIT; y : OUT BIT); END COMPONENT;
Explanation: For a 2 input OR gate, there must be 2 inputs and only one output. Therefore, some options are legal. But, the name of component can’t be same as any reserved word of VHDL. Therefore, a name of component can’t be ‘or’.
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