This set of Basic VHDL Questions and Answers focuses on “Implementing Gates with Different Modelling – 2”.
1. What is the minimum number of NAND gates required to implement an EXOR gate?
Explanation: We can implement an EXOR gate with a minimum of 4 NAND gates. However, when we follow the conventional way to convert an EXOR logic into the NADN logic, then the number of logic gates required is 5, but 1 of them is redundant and therefore, we can implement EXOR get by using 4 NAND gates.
2. Which of the following logic describes the EXOR gate?
a) y <= ((not a) OR (not b)) AND ((not a) OR (not b));
b) y <= ((not a) OR b) AND (a OR (not b))
c) y <= ((not a) AND (not b)) OR ((not a) AND (not b));
d) y <= ((not a) AND b) OR (a AND (not b));
Explanation: EXOR function or Exclusive OR is a function in which two inputs of the gate can’t be at high level exclusively, in that case the output will be low. It is described by Y = A’B + AB’. This function is described in the VHDL terms by using option d. Therefore, option d represents EXOR gate.
3. What logic circuit is described by the following code?
ARCHITECTURE gate OF my_gate IS BEGIN WITH ab SELECT y<= 0 WHEN “01” OR “10”; 1 WHEN OTHERS; END gate;
Explanation: Since the output is high when all the two inputs are either high or low. Otherwise, the output is low. This is the case opposite of EXOR gate. So, this must be EXNOR gate.
4. Sometimes gates modeled with ________ modeling may behave differently.
d) Structural and Behavioral
Explanation: Sometimes, dataflow modeling doesn’t behave as we want it to. This different behavior can be with any of the gate. For example, OR gate may behave as AND gate for instance. This occurs at the time of synthesis due to switches in the switch bank.
5. The odd behavior of gates in dataflow modeling may be the result of ________
a) Sequential statements
b) Wrong logic definitions
d) Inappropriate assignments
Explanation: The VHDL code is concurrent code and it has its own advantages and disadvantages. Concurrency of VHDL results in faster execution. In some PAL or PLA device, it may be like executing AND after OR execution which may result in different results.
6. Which of the following option represents a structural model for not gate?
Architecture not_gate OF my_func IS BEGIN x: IN STD_LOGIC; y: OUT STD_LOGIC; END not_gate;
Architecture not_gate OF my_func IS BEGIN x: IN STD_LOGIC; y: OUT STD_LOGIC; y<= NOT x; END not_gate;
Architecture not_gate OF my_func IS BEGIN COMPONENT NOT IS Port( x: IN STD_LOGIC; y: OUT STD_LOGIC); END COMPONENT; END not_gate;
Architecture not_gate OF my_func IS BEGIN COMPONENT not1 IS PORT( x: IN STD_LOGIC; y: OUT STD_LOGIC); END COMPONENT; END not_gate;
Explanation: Since the structural modeling defines only the components with their input and output ports. But the name of component can’t be same as any reserved word of VHDL.
7. In CPLD, there are many input switches arranged in a switch bank, if an AND gate is behaving oddly but could be the reason?
a) Incorrect interconnections
b) Concurrent execution of statements
c) Mismatch of ports name and switches
d) Wrong libraries included
Explanation: A CPLD is a device which has many input outputs and logic gates and it also includes interconnection between them. The inputs are arranged in the form of switch banks, the gate may perform different due to concurrency of statement. Due to concurrent statements, the state of a switch can vary and which can affect the output.
8. For gates, which of the following modeling style will corresponds to shortest code?
b) Data flow
d) Both data flow and behavioral
Explanation: Since in case of dataflow modeling we just need to define the relation between inputs and outputs using some logical function. So, gates can be modeled be using dataflow style in just one line. Whereas Behavioral needs selected assignment and structural used component declaration and instantiation.
9. Generally structural modeling is used with another modeling style.
Explanation: We can’t describe a logic gate or circuit by using a structural model alone. At least one more architecture is needed to properly describe the behavior of the circuit. So, generally more than one architectures are used.
10. Which of the following doesn’t corresponds to NAND gate?
y <= NOT( a AND b)
y <= NOT a OR NOT b
y <= NOT a AND NOT b
WITH ab SELECT y <= 0 WHEN ”11” 1 WHEN OTHERS
Explanation: Option a corresponds to NAND gate and option d is also the truth table of NAND gate. Now in option b, the gate described is bubbled OR gate which is equivalent to NAND gate. Option c corresponds to bubbled AND which is equivalent to NOR gate.
Sanfoundry Global Education & Learning Series – VHDL.
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