# VHDL Questions and Answers – Implementing Combinational Circuits with VHDL – 2

This set of Tough VHDL Questions and Answers focuses on “Implementing Combinational Circuits with VHDL – 2”.

1. The process statement used in combinational circuits is called ______ process.
a) Combinational
b) Clocked
c) Unclocked
d) Sequential

Explanation: The process, in which no clock signal is used, is called a combinational process. In a combinational process, the sensitivity list doesn’t include any clock signal for synchronization. In the case of sequential circuits the clock signal is used.

2. Why we need to include all the input signals in the sensitivity list of the process?
a) To monitor the output continuously
b) To monitor the input continuously
c) To make the circuit synthesizable by EDA tools
d) No special purpose

Explanation: If the input signals are not in the sensitivity list of the process, then one can’t monitor the change in input. Any change in input signal will not change the output simultaneously by running the process again.

3. If only two bit vectors are allowed to use in the VHDL code, then how many number of MUX will be required to implement 4 to 1 MUX?
a) 1
b) 2
c) 3
d) 4

Explanation: Since we have inputs with two bits only, so we can use 2 to 1 MUX to implement the required design. So, to design 4 to 1 MUX, we need 3 2 to 1 MUX and hence we can get the desired circuit by using 3 multiplexers.

4. A package is designed called mux4to1_package, in which a component called mux4to1 is defined, which is a 4 to 1 multiplexer. Now a user wants to design a 16 to 1 MUX by using the same component only, how many times he needs to use the PORT MAP statement?
a) 2
b) 3
c) 4
d) 5

Explanation: The problem statement says that a 16:1 MUX is to be designed by using 4:1 multiplexers only. This can be done by using 5 numbers of 4 to 1 multiplexers. Here, 4 MUXs are required to collect all the inputs and one is used to select one from the 4 multiplexers outputs.

5. In designing a 2 to 1 demultiplexer with input d, output y and select line s, which of the following is a correct process statement?
a) PROCESS(d)
b) PROCESS(d(0), d(1), s)
c) PROCESS(d(0), d(1))
d) PROCESS(d, s, y)

Explanation: In a combinational process, the sensitivity list must include all the inputs. For a 2 to 1 MUX, there must be 2 inputs which are d(0) and d(1); also the process should be sensitive to the select line, so s also should be in the sensitivity list.
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6. The given code represents a convertor. Which kind of convertor it is?

```ENTITY convert IS
PORT(b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
x : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END convert;
ARCHITECTURE convertor OF covert IS
BEGIN
PROCESS(b)
BEGIN
CASE b IS
WHEN “0000” => x <= “1111110”;
WHEN “0001” => x <= “0110000”;
WHEN “0010” => x <= “1101101”;
WHEN “0011” => x <= “1111001”;
WHEN “0100” => x <= “0110011”;
WHEN “0101” => x <= “1011011”;
WHEN “0110” => x <= “1011111”;
WHEN “0111” => x <= “1110000”;
WHEN “1000” => x <= “1111111”;
WHEN “1001” => x <= “1110011”;
WHEN OTHERS => x <= “0000000”;
END CASE;
END PROCESS;
END convertor;```

a) Gray to BCD
b) 7 segment to BCD
c) BCD to gray
d) BCD to 7 segment display

Explanation: Clearly, it is a BCD to 7 segment display convertor. This circuit takes a 4 bit BCD input and convert it into 7 bits output which may be used for LED output and hence the 7 segment display can be operated.

7. What is the function of the below code?

```ENTITY my_logic IS
PORT (din : STD_LOGIC_VECTOR(7 DOWNTO 0);
Count : STD_LOGIC_VECTOR(3 DOWNTO 0));
END my_logic;
ARCHITECTURE behavior OF my_logic IS
BEGIN
Count <= “0000”
PROCESS(din)
BEGIN
L1: FOR i IN 0 TO 7 LOOP
IF(din(i) = ‘1’) THEN
Count = count+1;
ELSE
NEXT L1;
END LOOP;
END PROCESS;
END behavior;```

a) To count number of ones in the given data
b) To count number of zeroes in the given data
c) To reverse the order of given data
d) To perform binary multiplication of two data inputs

Explanation: Because a loop is used and din is monitored for every bit. If any bit in the din is one then the counter is incremented by one. Therefore, the code is counting the number of ones in a given vector of bits.

8. What will be the value of count output, if the data din is 11001111?

```ENTITY my_logic IS
PORT (din : STD_LOGIC_VECTOR(7 DOWNTO 0);
Count : STD_LOGIC_VECTOR(3 DOWNTO 0));
END my_logic;
ARCHITECTURE behavior OF my_logic IS
BEGIN
Count <= “0000”
PROCESS(din)
BEGIN
L1: FOR i IN 0 TO 7 LOOP
IF(din(i) = ‘1’) THEN
Count = count+1;
ELSE
NEXT L1;
END LOOP;
END PROCESS;
END behavior;```

a) 6
b) 0110
c) 2
d) 0010

Explanation: The count is a signal of bit vector type and hence the output will be a stream of bits. In this case there are 6 ones in the input, which corresponds to 0110 in the binary number system.

9. In the combinational process, the use of output signal in the sensitivity list is illegal.
a) True
b) False

Explanation: Though it is not illegal to use any output signal in the combinational process; but it is not good practice to do. The change in output will cause the process to run again which is not desirable. We can use the output signal in sensitivity list but it will not give desirable results.

10. A parity generator is a combinational circuit and is designed by using a combinational process.
a) True
b) False

Explanation: A parity generator is a combinational circuit since its output depends on the present input only. Also, no clock signal is required to implement and synchronize the parity generator so it can be implemented by combinational process.

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