This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Assert Statement”. 1. Assert statement is a _____________ statement. a) Concurrent and synthesizable b) Sequential and synthesizable c) Concurrent and Non-synthesizable d) Sequential and Non-synthesizable 2. What is the use of assert statement in VHDL? a) To print any string b) To check … Read more
This set of VHDL Multiple Choice Questions & Answers focuses on “LOOP Statement – 2”. 1. The correct syntax for using EXIT in a loop is ___________ a) EXIT loop_label WHEN condition; b) EXIT WHEN condition loop_label; c) loop_label WHEN condition EXIT d) EXIT WHEN loop_label condition 2. FOR loop uses a loop index, the … Read more
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “LOOP Statement – 1”. 1. A loop statement is used where we needs to ________ a) Select one from many choices b) Check a condition c) Repeat the statements d) Choose one from two cases 2. Loop is a ________ statement. a) Concurrent … Read more
This set of VHDL MCQs focuses on “Case Statement – 2”. 1. If one wants to perform no action, when any condition is true, then which of the following keyword can be used? a) NO OPERATION; b) NOP; c) NULL; d) NEXT; 2. It is not possible to use range with _________ types. a) Integer … Read more
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Case Statement – 1”. 1. What is the problem with IF statement? a) Overlapping of conditions b) No default value c) The condition can be Boolean only d) Restriction on number of ELSE statement 2. In which of the following statements, all the … Read more
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “IF Statement”. 1. What kind of statement is the IF statement? a) Concurrent b) Sequential c) Assignment d) Selected assignment 2. Which of the following keyword is not associated with IF statement? a) ELSE b) THEN c) ELSIF d) WHEN 3. Which of … Read more
This set of VHDL Quiz focuses on “Process Statement – 2”. 1. It is possible to use sensitivity list and wait statements in the same process. a) True b) False 2. The process can be __________ by using WAIT statements. a) Suspended b) Resumed c) Suspended as well as resumed d) Cannot be determined 3. … Read more
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Process Statement – 1”. 1. Process is a _______ statement. a) Concurrent b) Sequential c) Delay d) Both concurrent and sequential 2. If there is more than one process in a VHDL code, How they are executed? a) One after the other b) … Read more
This set of VHDL test focuses on “Signal Assignment – 2”. 1. The selected concurrent statement is equivalent to ________ sequential statement. a) If else b) Loop c) Wait d) Case 2. Those statement which are placed under ________ are concurrent. a) Process b) Function c) Architecture d) Procedure 3. In case of concurrent assignment, … Read more
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Signal Assignment – 1”. 1. The signal assignment is considered as a ________ a) Concurrent statement b) Sequential statement c) Subprogram d) Package declaration statement 2. How can we use an assignment statement as a sequential assignment? a) By using keyword WAIT b) … Read more
