This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Structural Modelling – 1”.
1. Which of the following is defined in structural modeling?
a) The structure of circuit
b) Behavior of circuit on different inputs
c) Data flow from input to output
d) Functional structure
View Answer
Explanation: Structural modeling is the modeling of the circuit at the component level. This type of modeling is used to describe the structure of the system with all the components. Along with components, interconnections between them are also defined.
2. Which of the following is not a way of partitioning a design?
a) Component
b) Block statement
c) Processes
d) Generics
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Explanation: A VHDL design can be partitioned in many ways but generics is not the way to partition the design. Generics are used as constants. A component can divide the design at a structural level. Similarly, Blocks and processes can divide the behavioral model of the design.
3. What is the basic unit of structural modeling?
a) Process
b) Component declaration
c) Component instantiation
d) Block
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Explanation: Structural modeling describes the design at the component level. Like behavioral modeling is described by using processes, similarly, structural modeling is described by using component instantiation. Both processes and component instantiation are described in the architecture body.
4. Which of the following is similar to the entity declaration in structural modeling?
a) Component instantiation
b) Component declaration
c) Port map
d) Generic map
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Explanation: Component declaration in structural modeling is similar to the entity declaration. It describes the external interface of the component or subcomponent. All the input and output ports are declared in the component declaration part.
5. What do you mean by component instantiation?
a) To use the component
b) To describe external interface of the component
c) To declare the gate level components
d) To remove any component from the design
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Explanation: Component instantiation means to use the component in the circuit. Declaration of component just declares the input and outputs of the component but its instantiation describes its interconnection with other components and to port it in the circuit.
6. The structural model is similar to___________
a) Boolean relations of the circuit
b) Schematic block diagram of the circuit
c) Timing relations of the circuit
d) Components of the circuit
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Explanation: The structural modeling in VHDL is similar to the schematic block diagram of the circuit. Just like block diagram defines the components and interconnection between them, same is the case with structural modeling.
7. Which of the following is correct syntax for component declaration?
a)
COMPONENT component_name IS PORT ( port_mode : type port_name; port_mode : type port_name; ….); END component_name;
b)
COMPONENT component_name IS PORT ( port_mode : type port_name; port_mode : type port_name; ….); END COMPONENT;
c)
COMPONENT component_name IS PORT ( port_name : mode type; port_name : mode type; ….); END component_name;
d)
COMPONENT component_name IS PORT ( port_name : mode type; port_name : mode type; ….); END COMPONENT;
Explanation: To define a component in the code, the keyword COMPONENT is used followed by the name of the component and keyword IS. In the next lines, the ports of the component are declared and the end is done with END keyword followed by the keyword COMPONENT.
8. Which of the following is the correct syntax for component instantiation?
a) instantiate : component_name PORT MAP (port_list);
b) label : instantiate COMPONENT PORT MAP (port_list);
c) label : component_name PORT MAP (port_list);
d) label : instantiate component_name PORT MAP (port_list)
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Explanation: Component instantiation is done in the architecture part by using some label and the function called PORT MAP(). The name of the component is followed by the function PORT MAP (). The arguments list of the function contains the name of ports in the same order as they were declared. By using this we can define the interconnection between ports.
9. It is possible to use a component twice which was declared only once.
a) True
b) False
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Explanation: There is no restriction on the number of times a component can be used whose declaration is done. It is needed to be declared only once. Just using two or more different labels, we can use the same component again and again.
10. Which of the following must be known to describe a structural model in VHDL?
a) Number of inputs and outputs
b) Components and their connections
c) Relation between inputs and outputs
d) Value of output for different input combinations
View Answer
Explanation: It is necessary to know the whole circuit at the component level and how these components are interconnected with each other. Since structural model describes the input and output ports of a design, so we need the components and their connections.
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