This set of VHDL Questions and Answers for Campus interviews focuses on “Functions and Subprograms – 3”.
1. In VHDL it is not possible to use recursive functions.
Explanation: Like all other traditional programming languages, in VHDL too we can use recursive functions. Recursive function is the function which calls itself again and again until a condition comes to be true. It is possible to call functions recursively.
2. Apart from using WAIT statements, which of the following is not possible in functions?
a) Variable assignment
b) Return statement
c) Variable declaration
d) Signal assignment
Explanation: The signal assignment can’t be done inside a function body. It is possible to declare a variable and assign it some value but it is not possible to declare and use signal assignment inside the function.
3. Conversion functions are used to _________
a) Resolve value of a signal with multiple drivers
b) Convert one data type into another
c) Convert one data object into another
d) Resolve value of a constant with multiple drivers
Explanation: Conversion functions are the functions which are used to convert any object of one data type into another data type. Some of such conversion functions are predefined in the packages. For example, CONV_INTEGER() converts the parameter into an integer value.
4. The variables declared inside a function retain their values between two function calls.
Explanation: A function may declare local variables which are accessible inside the function only. These variables don’t retain their values between successive calls but are reinitialized each time the function is called.
5. The minimum number of parameters that must be there in a function is _____
Explanation: Yes, It is possible to have a function which has no parameter specified in the parameter list. If we don’t need to pass any information to the function from the main code, then there is no need to use any parameter in the list.
6. Which of the following is not the legal name of a function?
Explanation: As for all other identifiers, the name may not be any reserved word of VHDL and can have alphanumeric characters and an underscore sign. The only different thing with functions is that the name of function can be any operator sign also.
7. In the following code, which of the lines corresponds to function call and function definition?
L1 : ARCHITECTURE adder OF adder IS L2 : BEGIN L3 : x <= sum ( SIGNAL a : STD_LOGIC; SIGNAL b : STD_LOGIC); L4 : END adder; L5 : FUNCTION sum ( SIGNAL a : STD_LOGIC; SIGNAL b : STD_LOGIC) RETURN STD_LOGIC IS L6 : VARIABLE c : INTEGER; L7 : BEGIN L8 : c<= a OR b; L9 : RETURN c; L10 : END sum;
a) L5, L3
b) L5, L9
c) L3, L7
d) L3, L5
Explanation: Function call is when a function is invoked as an expression and the definition of function is where the whole description of function is given. Therefore, L3 corresponds to a function call and L5 is where function definition starts.
8. What is the ease provided by using functions?
a) Easy debugging
b) Easy reading
c) Easy calling
d) Easy implementation
Explanation: Using function results in easy debugging. Since reading and maintaining code is easy while using functions. Usually, the architecture of a code is very big and therefore, causes difficulty in debugging. So, by using functions, debugging is easy.
9. If a function has an operator sign as its name, then what will be the purpose of that function?
d) Define the data type
Explanation: When we want to make any operator behave differently, then we can define a function whose name will be same as the operator. This process of using an operator in different manner is called the operator overloading.
10. What is the alternative for specifying the vector size in the function?
a) Not using arrays
b) Defining every single element differently
c) Defining a subtype
d) Using bit vector
Explanation: Sometimes, it is necessary to use arrays. In functions, it is not possible to define the size of array or vector we are using. Instead, we can define a subtype for the same which can be used easily as a parameter to the function.
Sanfoundry Global Education & Learning Series – VHDL.
To practice all areas of VHDL for Campus Interviews, here is complete set of 1000+ Multiple Choice Questions and Answers.