# VHDL Questions and Answers – Type of Delays in Behavioural Modelling

This set of VHDL Objective Questions & Answers focuses on “Type of Delays in Behavioural Modelling”.

1. Which of the following is default delay in VHDL?
a) Inertial delay
b) Transport delay
c) Delta delay
d) Wire delay

Explanation: In VHDL, inertial delay is the default delay in VHDL. If no delay type is specified then it will be used as inertial delay. The reason behind taking, inertial delay as default is that in most case it behaves similarly to the actual device to be designed.

2. What must be overcome by the output signal to change the value in case of inertial delay?
a) Time
b) Error
c) Inertia
d) Pulse

Explanation: In case of inertial delay model, the output signal has some inertia which must be overcome for the signal to change its value. If a signal value is maintained for a time longer than the delay through the device, the output signal value changes to a new state.

3. The inertia value in inertial delay model is equal to _________
a) Initial value
b) Delay
c) Input value at a specific time
d) Output value at a specific time

Explanation: The inertia value in inertial delay model is equal to the delay through the device. This value must be overcome first to change the signal state. If there is any impulsive change in between then the state of signal will not change after the specified delay.

4. Transport delay is a kind of __________
a) Synthesis delay
b) Simulation delay
c) Inertial delay
d) Wire delay

Explanation: Transport delay represents a wire delay in which any pulse is propagated to the output signal delayed by a specified delay value. Therefore, Transport delay is useful in modeling the delay line devices and path delays in ASICs.

5. In inertial delay, if the signal value is maintained for the time period less than delay tiem, then the signal value does not change.
a) True
b) False

Explanation: If there are any spikes or pulses in between the delay period then the output value doesn’t change accordingly. Because any pulse in between the delay period will be swallowed in case of inertial delay and the output state will not change.
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6. A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the inertial delay model is used?
a) 30 ns
b) 40 ns
c) 20 ns
d) Output will remain zero

Explanation: Inertial delay model swallows the pulses or spikes in between the delay time period. The buffer is executed at 0 ns for the delay of 20 ns and then the value of A changes at 10 ns, which again execute buffer and schedule the output to be 1 at 30 ns. But at 20 ns, the value of A again changes which executes the buffer again and schedule the output to be zero at 40 ns. Therefore, the output will not change. Inertial model doesn’t order events it will take into consideration only the last event.

7. The keyword TRANSPORT in any assignment statement specifies _______
a) Transport delay
b) Transfer the right operand immediately to left operand
c) Transporting the value of left operand to right operand
d) Inertial delay

Explanation: TRANSPORT is a keyword used for specifying the use of transport delay. The mechanism followed by the EDA tool will be the transport delay mechanism instead of the default delay type called inertial delay.

8. A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the transport delay model is used?
a) 20 ns
b) 30 ns
c) 40 ns
d) Output will remain zero

Explanation: In case of transport delay model, all the spikes and pulses, no matter how small, are taken into consideration i.e. not swallowed down. Transport delay order the events rather than just scheduling the last event. Therefore, when the buffer is executed at 10 ns, it will schedule a 1 at B at 30 ns. After which, it is again executed at 20 ns and hence the output will be zero again at 40 ns.

9. In the VHDL code given below, which delay model is used?

```LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY buffer IS
PORT(a : IN STD_LOGIC;
b : OUT STD_LOGIC);
END buffer;
ARCHITECTURE buf OF buffer IS
BEGIN
b <= a AFTER 20 ns;
END buf;```

a) Simulation delta model
b) Transport delay model
c) Inertial delay model
d) Multiple driver delay model

Explanation: The assignment statement b <= a AFTER 20 ns is a delay statement. As there is no delay type specified, consequently, it will be considered as inertial delay. If one wants to use transport delay model, then it needs to be specified unlike inertial delay. For example, b < TRANSPORT a AFTER 20 ns; this statement will introduce transport delay mechanism.

10. Following waveform shows the output B of a buffer having delay 10 ns for two different delay mechanisms, specify the name of delay mechanism for corresponding waveform.

a) W1- Inertial, W2- Transport
b) W1- Inertial, W2- Inertial
c) W1- Transport, W2- Transport
d) W1- Transport, W2- Inertial

Explanation: W1 is transport since it doesn’t need to overcome the inertia and the events are scheduled sequentially after the specified delay time period. Whereas, in waveform W2, the output is concerned with the last value only. Therefore, waveform 2 is the illustration of inertial delay model.

11. For zero delay events, which of the following mechanism is used?
a) Transport delay mechanism
b) Inertial delay mechanism
c) Delta delay mechanism
d) Preemption delay mechanism

Explanation: For zero delay events, The output can disparate between two different simulation runs. For example, in a complex circuit, if we are using a NAND gate then the output can be affected by the order of the events, like AND operation first and after that NOT operation can produce some different result whereas it opposite order can produce some different result. Therefore, to avoid this at the time of simulation, we use the simulation delta delay model.

12. Which of the following delay model follows the principle of preemption?
a) Inertial delay
b) Transport delay
c) Delta delay
d) Wire delay

Explanation: Preemption technique means that only last event is taken into consideration whereas preceding events can be ignored. Same is the case with inertial delay model in which only last value of output is considered ignoring all the previous events or pulses or spikes etc.

13. Which of the following is not the application of inertial delay?
a) Buffer delay
b) PC wire line delay
c) Simple delay in OR gate
d) Inverter delay

Explanation: The inertial delay can be used for any of the logic circuit may it be a logic gate or any combinational circuit, but it can’t be used in any wire. Because in wire line delay, we need to order event sequentially, this is possible only in transport delay mechanism. Therefore, PC wire line delay can be implemented only by using a transport delay mechanism.

14. The condition to implement the simulation delta delay is _______
a) All events must be synchronous
b) The events must have at least one sequential circuit
c) No condition
d) All events must be zero delay event

Explanation: The simulation delta delay model is used to solve the problem of different output for same input between different simulation runs. This occurs when all the events have zero delay and are not properly ordered. So, simulation delta delay model is implemented when the events are with zero delay.

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