This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Aliases and Qualified Expressions”.
1. What does an alias declaration actually do?
a) Creates a new object
b) Doesn’t create a new object
c) Creates a new signal
d) Overwrites a file
Explanation: An alias declaration is used for an alternative name for an existing object. An object is any signal, variable or constant. Thus, an alias creates a duplicate or xerox of the existing object but doesn’t create a new object.
2. Which of the following is the correct syntax for declaring an alias?
a) ALIAS alias_name : object_name;
b) ALIAS alias_name ; object_name;
c) ALIAS alias_name – alias_type object_name;
d) ALIAS alias_name : alias_type object_name;
Explanation: To declare an alias, the keyword ALIAS is used. Then, the colon sign followed by the name of ALIAS. Then, the name of the object is then specified whose alias is to be created. So, that the duplicate for that object can be created.
3. For what purpose in the following, one can use alias?
a) To divide the complex part into smaller slices
b) To decrease the simulation time
c) To make use of same memory
d) To assign different memory locations
Explanation: In the complex designs, for example, in the design of CPU, one may need to divide the complex part I to smaller reference slices which are easy to maintain and it also increases the readability of the code.
4. Which of the following can’t be aliased?
b) Loop variable
Explanation: All the objects from the VHDL can be aliased i.e. signals, variables, constants. Even all the non-objects can also be aliased except Labels, Loop parameters and Generate parameters. These are the only three exceptions.
5. An alias of array type can reverse the order of the array.
Explanation: It is possible to reverse the order of an array in its alias created. For example, if an array is defined with the range 0 TO 7, then its alias can also define 7 DOWNTO 0. It will be completely legal in VHDL.
6. In what way the qualified expression differs from a normal expression?
a) It has a keyword qualified in front of it
b) Its type is explicitly defined
c) Its range is defined
d) It is similar to simple expression but is synthesizable
Explanation: Qualified expression is an expression whose type is being explicitly specified in the expression itself. In some cases, it is necessary to specify the type other it may be ambiguous to interpret the expression.
7. Which of the following is the correct syntax to define a qualified expression?
a) (expression)’ type
b) (expression)” type
c) type’ (expression)
d) type” (expression)
Explanation: To define a qualified expression, first we need to specify the type which is followed by a single quotation mark. After specifying the type, then the expression is written.
8. Where one should use the qualified expression?
a) In all overloaded functions
b) In overloaded functions with different number of parameters
c) In overloaded functions with different parameter names
d) In overloaded functions with different parameter types
Explanation: When the parameters in two overloaded functions are of different type, then qualified expressions may be needed. In case of different number of parameters, it is easy to identify which function is called, to the user and to the simulation tool as well. But, if there are same number of parameters but different type, then the things may be ambiguous. So, there we need to specify the type of expression.
9. Which one of the following would be the best use of qualified expression?
a) Function overloaded with bit and integer types
b) Function overloaded with bit_vector and std_logic_vector
c) Function overloaded with bit_vector and std_logic
d) Function overloaded with std_logic_vector and bit
Explanation: In case of function overloading, where in one function the parameter is of bit_vector type and other is of std_logic_vector type, then it could be difficult to identify that which function is being called. Say, 0110 is the argument passed to function, one can’t identify its type by seeing. So, qualified expression must be used.
10. A qualified expression is synthesizable in VHDL.
Explanation: A qualified expression is usually supported by synthesis tools. So, qualified expression is synthesizable, the only condition is that it should use a type which can be synthesized.
Sanfoundry Global Education & Learning Series – VHDL.
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