This set of VHDL online quiz focuses on “Signal vs Variables – 2”.
1. Which data object can’t be declared inside a process?
Explanation: A process consists of sequential statements and signals can be used inside the process. But, it is not possible to declare a signal inside the process. Variables, on the other hand, can be declared in a process.
2. When a signal is assigned a value inside a process, then the value of a signal is updated _________
b) After one delta cycle
c) At the end of the corresponding process
d) At the end of architecture
Explanation: The signal is not updated immediately. The new value should not be expected to be ready before the conclusion of the corresponding process. It is updated at the end of the process and therefore, it is not recommended to assign two or more values to a signal in the same process since only last one is considered.
3. A variable is assigned a value inside a process, the new value of the variable will be available_______
a) After one delta cycle
c) At the end of a process
d) At the end of architecture
Explanation: Unlike signals, the value of variable is updated immediately. In other words, we can say that the new value of the variable or its updated value can be used immediately in the next line of the code which is not the case with variables.
4. A variable can be used outside the process i.e. in the architecture.
Explanation: A variable can be used inside a process, function or procedure only. One can’t use it outside the process. The variables can’t be assigned values concurrently or in a parallel manner as we can do with the signals.
5. There are no delays in case of variables.
Explanation: As we know that the variables get their value at the same time or immediately. No delay can be used in the variable assignment. However, in signals there are two types of delay which are transport and inertial delays. This is not possible to use AFTER keyword in the variable assignment.
6. When there is no delay specified in a signal assignment (concurrent), the delay will be _______
b) Transport delay
c) Inertial delay
d) Delta delay
Explanation: In a concurrent assignment statement either transport or inertial delay is used. Even if there is zero delay specified it will consider delta delay before assigning a value to the signal. So, it is not possible to assign the value to signal immediately even if no delay is specified.
7. During synthesis, a variable infers ________
a) Flip flop
d) Variables are not synthesizable
Explanation: Both signal and variable are synthesizable and variable infers a wire at the time of synthesis. However, the signal, unlike variable, infers a flip flop at the time of synthesis.
8. In which of the following, the right hand side of an assignment is a waveform element?
Explanation: The right hand side of a signal assignment statement is a sequence of waveform elements. These elements are having associated time expressions or delays which are generally followed by AFTER keyword.
9. Which of the following needs no evaluation of drivers?
Explanation: Signals have drivers associated with them which need evaluation and resolution (in case of multiple drivers). On the other hand, variable has no driver associated so no evaluation is required at the time of simulation. So, variables are cheaper to implement as compared to signals.
10. What is there in right hand side of a variable assignment?
a) Time expressions
b) Waveform elements
d) Simple expressions
Explanation: Unlike signals, there are no waveform elements and timing expressions on the right hand side of a variable assignment. The right hand side of a variable assignment is always an expression which can be any of the Boolean, arithmetic or logical.
Sanfoundry Global Education & Learning Series – VHDL.
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